Odd-Even Command/Address Sampling Circuit for DDR5 Timing Skew
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Solution Overview
Problem
In semiconductor memory devices like DDR5 DRAM, there is a timing sequence skew between command and address signals due to the need for two clock cycles, leading to errors and increased circuit area requirements.
Innovation Solution
A signal sampling circuit that includes an input sampling circuit, logical operation circuit, command decoding circuit, and output combined circuit to align the timing sequences of command and address signals using odd and even clock signals, reducing the number of address buses and avoiding skew under varying PVT conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the CA signal is designed to be a signal of two clock cycles to achieve higher data transmission speed, then the data transmission speed is improved, but a timing sequence skew occurs between the address signal and the command signal
Solution Approach 1:
The patent divides the CA signal into separate address signal and command signal paths, and further segments the clock signal into odd and even clock cycles. This segmentation allows independent timing control of address and command signals, resolving the timing skew issue while maintaining high data transmission speed through dual-clock-cycle operation
Solution Approach 2:
The patent introduces a sampling circuit as an intermediary component that uses odd and even clock signals to separately sample the address and command signals. This intermediary sampling mechanism synchronizes the timing of both signal types, eliminating timing sequence skew while preserving the benefits of two-clock-cycle operation
2Productivity
If a large number of address buses are used to handle the CA signal, then the data transmission capability is improved, but the circuit area increases
Solution Approach 1:
The patent merges the odd and even address signals into a unified address bus structure. By combining the sampling results from odd and even clock cycles through the output combining circuit, the system achieves high data transmission capability with reduced circuit area, as the merged address bus serves both clock cycle domains
Data Source
AI summary
A signal sampling circuit and a semiconductor memory are provided. The signal sampling circuit includes: an input sampling circuit, configured to sample a first CS signal and a first CA signal according to a first clock signal to obtain a second CS signal and a second CA signal; a logical operation circuit, configured to perform a logical operation on the first clock signal and the second CS signal; a command decoding circuit, configured to decode and sample an initial command signal according to the second CS signal and the CS clock signal; and an output combined circuit, configured to: sample the second odd CA signal and the second even CA signal according to the even CS clock signal and the odd CS clock signal; and sample the second odd CA signal and the second even CA signal according to the odd CS clock signal and the even CS clock signal.