RRAM Cell Arrays with Variable Dielectrics for Mixed Endurance
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Solution Overview
Problem
Conventional RRAM devices require multiple fabrication recipes and additional time/cost to produce cells suitable for different applications with varying endurance levels, lacking efficiency in integrating multiple applications on a single chip.
Innovation Solution
A novel RRAM architecture with integrated RRAM cell arrays, utilizing a single recipe to form variable resistance dielectric layers with different thickness and crystalline structures, allowing for multiple applications by configuring pairs of RRAM cell arrays to present complementary logic states and using a universal dielectric layer for different endurance needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple fabrication recipes are used to produce RRAM cells for different applications, then cells with different endurance levels can be produced, but fabrication time and cost increase
Solution Approach 1:
A single fabrication recipe is designed to produce variable resistance dielectric layers that can serve multiple applications with different endurance requirements. The universal recipe uses atomic layer deposition to form dielectric layers with controlled thickness and crystalline structure that can be configured for various endurance levels without requiring separate fabrication processes for each application.
Solution Approach 2:
The invention changes physical parameters of the dielectric layer (thickness, crystalline structure) within a single fabrication recipe to achieve different endurance levels. By adjusting deposition conditions and layer thickness during the atomic layer deposition process, the same fabrication recipe can produce dielectric layers optimized for different application requirements.
2Adaptability or versatility
If multiple fabrication recipes are used to produce RRAM cells for different applications, then cells with different endurance levels can be produced, but fabrication cost increases
Solution Approach 1:
A single fabrication recipe is designed to produce variable resistance dielectric layers that can serve multiple applications with different endurance requirements. The universal recipe uses atomic layer deposition to form dielectric layers with controlled thickness and crystalline structure that can be configured for various endurance levels without requiring separate fabrication processes for each application.
Solution Approach 2:
Multiple application-specific dielectric layer configurations are merged into a single fabrication recipe. The process combines the capabilities of producing different endurance levels, thicknesses, and crystalline structures into one integrated atomic layer deposition process, eliminating the need for separate fabrication lines or recipes for each application.
3Adaptability or versatility
If multiple fabrication recipes are used to produce RRAM cells for different applications, then cells with different endurance levels can be produced, but process complexity increases
Solution Approach 1:
A single fabrication recipe is designed to produce variable resistance dielectric layers that can serve multiple applications with different endurance requirements. The universal recipe uses atomic layer deposition to form dielectric layers with controlled thickness and crystalline structure that can be configured for various endurance levels without requiring separate fabrication processes for each application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of RRAM cells on a single chip for diverse applications with varying endurance requirements without additional fabrication steps, enhancing efficiency and reducing costs.
Implementation Method 1
RRAM devices operate under the principle that a dielectric, which is normally insulating, can be made to conduct through a filament or conduction path formed after the application of a sufficiently high voltage
Implementation Method 2
Once the filament or conduction path is formed, it may be reset, i.e. broken, resulting in a high resistance state (HRS) or set, i.e. re-formed, resulting in a lower resistance (LRS), by an appropriately applied voltage
Data Source
AI summary
A method includes causing a first information bit to be written into a first bit cell in a first plurality of bit cells as an original logic state of the first information bit. The method also includes causing a second information bit to be written into a second bit cell in a second plurality of bit cells as an original logic state of the second information bit. The method also includes causing a third information bit to be written into a third bit cell in a third plurality of bit cells as a logically complementary state of the first information bit.