Memory Array Common Addressing for Short-Circuited Lines
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Solution Overview
Problem
Existing memory devices face challenges in efficiently addressing short-circuiting errors between wiring lines, which conventional methods often require redundant wiring lines, increasing complexity and resource usage.
Innovation Solution
A memory device design that assigns a common address to short-circuited wiring lines, allowing them to share a drive signal, thereby reducing the need for redundant wiring lines and enhancing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to address short-circuiting errors, then wiring lines can be replaced, but redundant wiring lines are required which increases device complexity
Solution Approach 1:
The patent merges multiple short-circuited wiring lines into a single logical unit by assigning them a common address. Instead of treating each short-circuited line as a separate entity requiring individual redundancy, the invention combines them so that one drive signal controls multiple physical wiring lines, thereby reducing the total number of wiring lines needed while maintaining error correction capability
Solution Approach 2:
The patent makes a single drive signal universal by enabling it to control multiple wiring lines simultaneously. The address assignment circuit is designed to output a common drive signal that can be applied to multiple short-circuited wiring lines, allowing one signal to serve multiple functions and reducing the overall complexity of the wiring structure
2Reliability
If redundant wiring lines are added to handle short-circuits, then reliability improves, but the device structure becomes more complex
Solution Approach 1:
The invention combines multiple short-circuited wiring lines into a single addressable unit. By assigning a common address to all short-circuited lines, the system treats them as one logical entity, eliminating the need for separate redundancy structures for each line and simplifying the overall wiring architecture while maintaining reliability
Solution Approach 2:
The patent converts the harmful effect of short-circuits into a beneficial feature by deliberately grouping short-circuited wiring lines together and assigning them a common address. Instead of viewing short-circuits as defects to be individually corrected, the invention embraces them as a condition that can be managed through unified address assignment, thereby simplifying the device structure
3Measurement precision
If each wiring line is assigned a unique address, then addressing precision is maintained, but the number of addresses increases with short-circuited lines
Solution Approach 1:
The patent merges the addressing of multiple short-circuited wiring lines into a single common address. Instead of assigning unique addresses to each short-circuited line (which would increase the total number of addresses), the invention combines them under one address, reducing the address space required while maintaining the ability to precisely control and access the memory cells connected to these lines
Data Source
AI summary
According to one embodiment, a memory device includes a plurality of first wiring lines each extending in a first direction, a plurality of second wiring lines each extending in a second direction, a plurality of memory cells provided between the first and second wiring lines, each including a variable resistance memory element and a switching element connected to each other in series, and an address assignment circuit assigning addresses to the first wiring lines, respectively. When the first wiring lines include a first short-circuited wiring line and a second short-circuited wiring line that are short-circuited to each other, the address assignment circuit assigns a common address to the first and second short-circuited wiring lines.