Variable Resistance Memory Fabrication with Matched Etch Selectivity
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Solution Overview
Problem
The challenge in fabricating variable resistance memory devices lies in the differential etch profiles that occur during the simultaneous formation of contact holes in the cell and peripheral areas due to the use of materials with different etch selectivities, which complicates the formation of consistent etch profiles and increases the risk of leakage currents.
Innovation Solution
The method involves forming mold insulation layers using materials with similar etch selectivity in both the cell and peripheral areas, and strategically removing the capping layer in specific regions to ensure uniform etch profiles, thereby facilitating the formation of consistent contact holes and reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If materials with different etch selectivities are used in cell area and peripheral area, then the etching process can be optimized for each area, but the etch profiles become inconsistent leading to manufacturing defects
Solution Approach 1:
The patent applies local quality by forming a removed capping layer structure that is present only in the peripheral area, not in the cell area. This localized modification allows the peripheral area to have different etching characteristics while maintaining material consistency overall. The removed capping layer creates a specific etch profile in the peripheral area that matches the cell area, resolving the inconsistency issue while preserving the benefits of area-specific optimization.
2Productivity
If simultaneous contact hole formation is performed in cell area and peripheral area, then production efficiency is improved, but etch profile differences cause leakage currents
Solution Approach 1:
The patent applies preliminary anti-action by pre-forming the removed capping layer structure in the peripheral area before the simultaneous etching process. This preliminary action counteracts the potential etch profile differences that would otherwise cause leakage currents during simultaneous contact hole formation. By preparing the peripheral area in advance with the appropriate capping layer configuration, the etching process produces consistent profiles across both areas, preventing leakage currents while maintaining high productivity.
3Adaptability or versatility
If different insulation layer materials are used in cell area and peripheral area, then area-specific performance is optimized, but process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the capping layer into two distinct segments: a retained capping layer in the cell area and a removed capping layer in the peripheral area. This segmentation allows each area to have optimized characteristics while using the same base material throughout. The segmented approach maintains material consistency and simplifies the overall process compared to using completely different materials, while still achieving area-specific performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of variable resistance memory devices with reduced etch profile differences, leading to improved integration and reduced leakage currents, enhancing the reliability and performance of the memory devices.
Implementation Method 1
forming a capping pattern on both sidewalls of the MTJ structure by anisotropically etching the capping layer in the cell area
Implementation Method 2
forming a buried insulation layer on the MTJ structure in the cell area and removing the capping layer from the peripheral area
Data Source
AI summary
According to the method of fabricating a variable resistance memory device, by forming a mold insulation layer from materials with similar etch selectivity in the cell area and the peripheral area, the difference between etch profiles that occurs during formation of the first contact hole and the second contact hole simultaneously in the cell area and the peripheral area may be reduced.