100G-KR Encoding With Burst Interleaving for Low-BER Ethernet
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Solution Overview
Problem
High-speed Ethernet networks, such as 100 G-KR, face challenges in maintaining low bit error rates and correcting burst errors effectively, as existing forward error correction schemes often compromise on latency, coding gain, and hardware complexity.
Innovation Solution
Implementing burst interleaving schemes and transcoding methods like 512B/514B and 256B/258B transcoding, combined with error correction codes like Reed-Solomon codes, to enhance error correction capabilities across multiple physical lanes in 100 G-KR networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward error correction schemes are implemented to achieve low bit error rates, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction process into multiple independent FEC codes operating on different data lanes. Each lane has its own FEC code, allowing parallel processing and reducing the complexity of any single code while maintaining overall reliability through the combination of multiple codes.
Solution Approach 2:
The patent introduces a new dimension of error correction by implementing burst interleaving across multiple lanes in addition to the traditional per-lane FEC. This multi-dimensional approach (per-lane FEC + cross-lane burst interleaving) provides comprehensive error protection without requiring overly complex single-code solutions.
2Reliability
If forward error correction schemes are implemented to correct burst errors, then reliability is improved, but latency increases
Solution Approach 1:
The patent divides burst error correction into two segmented stages: first, per-lane FEC codes handle errors within each lane independently and quickly; second, burst interleaving across lanes handles remaining burst errors. This segmentation allows each stage to operate efficiently with minimal latency while collectively providing strong burst error correction.
Solution Approach 2:
The patent applies preliminary FEC encoding to each lane before transmission, which handles the majority of errors proactively. The burst interleaving mechanism then handles any remaining errors that escape the first stage, creating a layered defense that reduces overall latency compared to using a single heavy-duty error correction code.
3Reliability
If forward error correction schemes are implemented to achieve low bit error rates, then reliability is improved, but net coding gain is compromised
Solution Approach 1:
The patent applies different error correction strategies to different parts of the data stream based on local error characteristics. Per-lane FEC provides strong protection for random errors in each lane, while burst interleaving provides targeted protection for burst errors affecting multiple lanes. This localized approach optimizes coding gain by applying the right level of protection where needed rather than uniformly across all data.
Solution Approach 2:
The patent implements partial error correction at the per-lane level with FEC codes, then applies additional partial correction at the cross-lane level with burst interleaving. This partial-action approach at multiple levels achieves comprehensive error correction with better net coding gain than a single excessive-action code would provide.
Data Source
AI summary
Aspects of a method and system for encoding in 100G-KR networking are described. In one example embodiment, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block, and encoding a data stream including the transcoded block.