Burst Error Correction TRIZ Cases
- Dynamic Parity Group FEC for Variable-Rate Satellite Links
Flexible matrix-based FEC uses parity tags and dynamic parity group lengths to recover missing blocks under variable satellite data rates.
- SD-LDPC Code Optimization for Burst Errors in 50G-PON Upstream
Intra-codeword interleaving and parity-check matrix rearrangement improve SD-LDPC BER under burst-mode upstream errors in 50G-PON.
- Constacyclic ECC Decoder for Burst and Multi-Bit Memory Errors
Global and local syndrome decoding lets a constacyclic ECC decoder correct burst and multi-bit memory errors with less reliability loss.
- ECC H-Matrix Grouping for Multi-Bit Memory Error Correction
Grouped and shifting H-matrix ECC helps memory systems correct multi-bit errors without miscorrection as capacity and defect risk increase.
- Streaming Code Frame Splitting for Partial Burst Loss Recovery
Frame splitting with adaptive parity and FEC-aware compression improves real-time recovery from partial burst packet losses in videoconferencing.
- ECC Syndrome Analysis for Adjacent Two-Bit Error Detection
Structured ECC syndrome analysis detects adjacent two-bit errors without extra parity bits, avoiding SEC miscorrection and added hardware.
- Memory Coding Circuit With Syndrome Error Boundary Detection
Three-syndrome decoding identifies error boundaries in memory codewords, correcting valid errors while preventing extra corruption beyond symbol limits.
- Latch Layout Interleaving for Multi-Bit Radiation Error Protection
Bounding-box latch grouping and location-aware ECC/BEC interleaving correct multi-bit radiation errors with lower circuit overhead.
- SECDED Error Coding With Burst Error Detection
A parity-check matrix extends SECDED coding to detect burst errors and reduce silent data corruption in IC data transmission.
- Hybrid Ethernet PHY FEC Switching for Latency and Burst Errors
Adaptive link training selects interleaved or non-interleaved RS-FEC to balance latency and burst-error resilience in 100 Gb/s Ethernet.
- Burst-Error Tolerant Decoder for High-Speed SerDes Links
Tests contiguous erasure patterns with RS decoding to correct burst and bit errors in high-speed SerDes transmission.
- Hybrid Ethernet PHY FEC Mode Selection for Latency and Burst Errors
Adaptive link training selects interleaved or non-interleaved RS-FEC to balance burst-error protection and latency in 100 Gb/s Ethernet links.
- DRAM ECC Circuit for Adjacent Two-Bit Error Correction
Selective bit shifting and parity grouping let DRAM ECC correct single-bit and adjacent two-bit cell errors, improving yield and reliability.
- LDPC Code Generation Using Trapping Set Cores for Error Floor Verification
Trapping set core detection and important sampling cut LDPC error floor verification time while enabling reliable low-error code generation.
- Burst-Error Tolerant Decoder Using Contiguous Erasure Patterns
Tests contiguous erasure patterns in encoded blocks to correct high-speed SerDes burst errors beyond conventional DFE and FEC limits.
- Memory Error Trapping Logic With Conditional Syndrome Capture
Capturing data, check bits, and error syndromes only when needed cuts staging registers, power dissipation, and memory debug uncertainty.
- LDPC Parity Mapping for Burst Errors in Defective Memory Cells
Maps second-type parity bits to bad memory cells so LDPC decoding handles burst errors with less throughput and power impact.
- Media Sector Realignment After Missed Sync Mark Detection
Anchor-point detection and retry re-reads realign a media sector after a missed sync mark, enabling user data recovery with less overhead.
- Memory ECC Layout for Consecutive Bit Error Correction
A split parity and ECC layout corrects two consecutive bit errors and detects four while reducing memory area, power, and performance overhead.
- Common-Mode Signaling for Burst-Error-Resistant Serial Links
Blockwise bit inversion with common-mode signaling cuts burst errors in high-speed serial links without large interleaver memory.