Burst-Error Tolerant Decoder for High-Speed SerDes Links
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Solution Overview
Problem
Conventional error correction techniques, such as Decision Feedback Equalization (DFE) and Forward Error Correction (FEC), are inadequate in addressing burst errors and bit-errors at high transmission rates in serial communication systems, particularly in SerDes interfaces, due to assumptions of error-free previous bits and limitations in correcting symbol errors.
Innovation Solution
The implementation of burst-error tolerant decoders that test all possible contiguous erasure patterns in a FEC block, using selection circuitry to identify a correction mask that best matches the burst-error output, and combining this with standard RS decoding to correct errors effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional error correction techniques (DFE and FEC) are used, then the system operates at high transmission rates, but burst errors and bit-errors cannot be effectively corrected
Solution Approach 1:
The patent segments the error correction process into multiple stages: first using DFE for initial error correction based on previous bits, then applying FEC for additional correction. This segmentation allows each stage to handle specific types of errors, with the combined approach capable of correcting burst errors that would overwhelm a single correction method operating alone.
Solution Approach 2:
The DFE performs preliminary error correction by assuming previous bits are error-free and using them to correct current bit errors. This preliminary action reduces the burden on the subsequent FEC stage, enabling the system to handle higher transmission rates while maintaining reliability through the layered correction approach.
2Device complexity
If DFE assumes error-free previous bits, then the decoding process is simplified, but correction fails when previous bits contain errors
Solution Approach 1:
The patent implements beforehand cushioning by having the DFE perform its best-effort correction first, creating a cushion of corrected bits that protects against error propagation. When DFE assumptions fail, the FEC stage provides additional protection, ensuring that occasional assumption violations do not catastrophically fail the entire correction process.
Solution Approach 2:
The FEC decoder acts as an intermediary between the DFE output and the final corrected data. It mediates by taking the partially corrected output from DFE and applying additional correction based on parity symbols, bridging the gap between simplified DFE operation and the need for high reliability when previous bits contain errors.
3Reliability
If standard FEC is used, then symbol errors can be corrected, but burst errors spanning multiple symbols cannot be effectively addressed
Solution Approach 1:
The patent merges DFE and FEC into a unified error correction system where both methods operate together. The DFE handles errors based on temporal relationships between bits, while FEC handles errors based on redundancy across symbols. This merging creates a versatile system capable of addressing both isolated symbol errors and extended burst errors that span multiple symbols.
Solution Approach 2:
The combined DFE-FEC system achieves multi-functionality by enabling the error correction mechanism to handle multiple error types: random bit errors, isolated symbol errors, and extended burst errors. This universal approach allows a single system to adapt to various error patterns without requiring separate correction mechanisms for each error type.
Data Source
AI summary
Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.