Memory Coding Circuit With Syndrome Error Boundary Detection
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Solution Overview
Problem
Conventional in-memory coding circuits using BCH coding technology face issues with error correction when errors exceed the error correction capability, leading to additional errors during incorrect correction, which the memory controller cannot handle.
Innovation Solution
A coding circuit with an encoder and decoder configuration that generates parity using a parity generating matrix and corrects errors based on first, second, and third syndromes to identify error boundaries, preventing additional errors from occurring beyond the error boundary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BCH coding technology is applied in the memory device, then 2-bit error correction capability is achieved, but additional errors occur when 3 or more bit errors exceed the error correction capability
Solution Approach 1:
The patent segments the error correction process into multiple stages: first using BCH coding for 2-bit error correction within each symbol, then using Reed-Solomon coding for additional error correction on a symbol-by-symbol basis. This segmentation allows the system to handle errors of varying magnitudes without generating additional errors, as each coding stage addresses specific error ranges appropriately.
Solution Approach 2:
The patent employs a composite coding approach by combining BCH coding and Reed-Solomon coding in a dual-coding structure. The BCH code provides 2-bit error correction capability while the RS code provides symbol-level error correction, creating a composite error correction system that maintains reliability even when error counts exceed the capability of either individual code alone.
2Reliability
If in-memory coding circuit is applied to double protect data, then error correction is enhanced, but memory controller cannot correct errors when additional errors exceed data symbol boundary
Solution Approach 1:
The patent implements dynamic error correction by enabling the memory controller to selectively apply Reed-Solomon decoding based on the number and distribution of errors detected. When errors are within correctable limits, the controller applies RS decoding; when errors exceed capabilities, the system gracefully handles the limitation without corrupting data beyond the symbol boundary, adapting the correction strategy to the actual error conditions.
3Measurement precision
If BCH coding corrects errors on symbol-by-symbol basis, then 1-symbol error correction is achieved regardless of error bits, but additional errors occur when error exceeds correction capability
Solution Approach 1:
The patent applies preliminary BCH coding at the memory device before data transfer to the memory controller. This preliminary error correction reduces the error burden on the memory controller, allowing it to focus on symbol-level Reed-Solomon correction. By performing initial error correction preliminarily, the system prevents uncorrected errors from propagating and causing additional errors at the controller stage.
Data Source
AI summary
A coding circuit includes an encoder circuit generating parity by applying input data to a parity generating matrix and generating an input codeword by concatenating the input data and the parity; and a decoder circuit detecting and correcting an error included in an output codeword based on a first syndrome, a second syndrome, and a third syndrome for identifying an error boundary. The first, second, and third syndromes are generated by applying the output codeword to the parity generating matrix.