ECC Syndrome Analysis for Adjacent Two-Bit Error Detection
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Solution Overview
Problem
Conventional error correction codes, such as Single Error Correction (SEC) codes, are limited in detecting two-bit errors and may introduce additional data corruption by misidentifying errors, requiring increased circuitry size and power consumption, and are not effective in detecting adjacent two-bit errors without additional parity bits.
Innovation Solution
The implementation of error correction code (ECC) logic that generates a syndrome vector using a parity checking matrix to detect adjacent two-bit errors without requiring additional parity bits, allowing for improved error detection without increasing hardware costs or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SEC codes are used for error correction, then one-bit errors can be corrected, but adjacent two-bit errors cannot be detected and may be misidentified as one-bit errors causing additional data corruption
Solution Approach 1:
The syndrome vector is segmented into multiple fields: a first field containing syndrome bits corresponding to original data bits, and a second field containing syndrome bits corresponding to parity bits. This segmentation allows independent analysis of different error patterns, enabling detection of adjacent two-bit errors that would otherwise be misidentified as single-bit errors.
Solution Approach 2:
The patent extends the error detection capability by adding an additional dimension to the syndrome vector analysis. By organizing syndrome bits into multiple fields and comparing patterns across these fields, the system can distinguish between single-bit errors and adjacent two-bit errors, effectively adding a new dimension to the error detection space without requiring additional parity bits.
2Reliability
If additional parity bits are added to detect adjacent two-bit errors, then error detection capability improves, but circuitry size and power consumption increase
Solution Approach 1:
The existing parity bits serve multiple functions: they enable both single-bit error correction and adjacent two-bit error detection through the structured syndrome vector analysis. The same parity checking matrix H is used to generate syndrome bits that contain information about both single-bit and two-bit error patterns, eliminating the need for separate error detection mechanisms.
Solution Approach 2:
The syndrome vector structure enables the system to self-diagnose error types. By examining the pattern of syndrome bits across different fields, the system automatically determines whether an error pattern corresponds to a single-bit error or an adjacent two-bit error, and takes appropriate corrective or detection actions without external intervention or additional hardware.
3Reliability
If additional parity bits are added to detect adjacent two-bit errors, then error detection capability improves, but power consumption increases
Solution Approach 1:
The existing parity bits serve multiple functions: they enable both single-bit error correction and adjacent two-bit error detection through the structured syndrome vector analysis. The same parity checking matrix H is used to generate syndrome bits that contain information about both single-bit and two-bit error patterns, eliminating the need for separate error detection mechanisms.
4Device complexity
If conventional SEC codes are used, then hardware implementation is simple, but adjacent two-bit errors are misidentified as one-bit errors
Solution Approach 1:
The syndrome vector is segmented into multiple fields: a first field containing syndrome bits corresponding to original data bits, and a second field containing syndrome bits corresponding to parity bits. This segmentation allows independent analysis of different error patterns, enabling detection of adjacent two-bit errors that would otherwise be misidentified as single-bit errors.
Solution Approach 2:
The patent extends the error detection capability by adding an additional dimension to the syndrome vector analysis. By organizing syndrome bits into multiple fields and comparing patterns across these fields, the system can distinguish between single-bit errors and adjacent two-bit errors, effectively adding a new dimension to the error detection space without requiring additional parity bits.
Data Source
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AI summary
In an embodiment, a processor includes error correction code (ECC) circuitry to: receive a codeword comprising data bits and parity bits; generate, using a parity checking matrix H, a syndrome vector associated with the received codeword, where the parity-checking matrix H comprises a data segment comprising N data columns and a parity segment comprising K parity columns, where a total quantity of data columns in the data segment with even weight is equal to N+K-2(K-1)+1; and detect an adjacent two bit error in the codeword based on a comparison of the syndrome vector to the parity checking matrix H. Other embodiments are described and claimed.