DRAM ECC Circuit for Adjacent Two-Bit Error Correction
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Solution Overview
Problem
The increasing bit errors in DRAM devices due to reduced fabrication design rules lead to decreased yield and require effective error correction mechanisms to enhance performance and reliability.
Innovation Solution
An error correction circuit for semiconductor memory devices, incorporating an ECC encoder and decoder, generates parity data and corrects single bit errors or two bit errors in adjacent memory cells using a parity check matrix, effectively gathering mis-corrected bits and multiple error bits in one symbol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fabrication design rules are reduced to increase integration density, then device capacity increases, but bit error rate increases and yield decreases
Solution Approach 1:
The main data is divided into multiple sub-data units (SDU1-SDU8), and the ECC code is segmented into corresponding code groups (CG1-CG8). This segmentation allows the error correction circuit to process and correct errors in each segment independently, improving reliability without requiring a complete redesign of the entire memory system.
Solution Approach 2:
An error correction circuit (ECC encoder and decoder) is introduced as an intermediary component between the memory cells and the external device. This intermediary generates parity data to detect and correct bit errors, thereby maintaining reliability despite reduced fabrication design rules.
2Reliability
If conventional ECC methods are used, then single bit errors can be corrected, but adjacent two bit errors cannot be corrected
Solution Approach 1:
The parity check matrix is designed with local quality characteristics where specific column vectors are configured to detect and correct adjacent two-bit errors. The matrix structure assigns different properties to different column vectors based on their position and relationship, enabling targeted error correction for adjacent errors without requiring a complete overhaul of the ECC system.
Solution Approach 2:
The ECC code structure combines multiple code groups (CG1-CG8) with different functions into a composite error correction system. This composite structure integrates both single-bit error correction capabilities and adjacent two-bit error correction capabilities, achieving enhanced reliability while managing complexity through modular design.
3Measurement precision
If mis-corrected bits are not gathered, then error correction is simpler, but error correction accuracy decreases
Solution Approach 1:
The column vectors in the parity check matrix are configured to gather mis-corrected bits and multiple error bits into one symbol. This merging approach consolidates error information, allowing the error correction circuit to identify and correct errors more accurately by analyzing concentrated error patterns rather than dispersed ones.
Data Source
AI summary
An error correction circuit includes ECC encoder and an ECC decoder. The ECC encoder generates, based on a first main data obtained by selectively shifting data bits of a main data based on a LSB of a row address, a parity data using an ECC and stores a codeword including the main data and the parity data in a target page. The ECC decoder generates a syndrome based on a second main data obtained by selectively shifting data bits of the main data based on the LSB of the row address, the parity data and a parity check matrix based on the ECC, and corrects a single bit error or corrects two bit errors when the two bit errors occur in adjacent two memory cells based on the syndrome. The mis-corrected bit is generated when the multiple error bits are present in the main data.