Memory Error Trapping Logic With Conditional Syndrome Capture
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Solution Overview
Problem
Large, dense memory structures like L3 cache are prone to errors, leading to increased power dissipation due to the need for multiple register stages in error trapping systems, and the uncertainty of when to capture error data complicates debugging and remedial actions.
Innovation Solution
Implementing error trapping logic circuits that receive data and check bits in one clock cycle to determine error presence and type in subsequent cycles, allowing conditional storage in trap registers based on operating mode, thereby reducing the number of staging registers and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipelining is used for memory access to improve throughput, then productivity is improved, but power dissipation increases due to additional register stages
Solution Approach 1:
The patent extracts the error detection function from the pipelined data path by implementing dedicated error detection logic that operates independently on read data. This allows error checking to occur without requiring additional pipeline stages, thereby maintaining throughput while reducing the power consumption associated with extensive pipelining register stages.
Solution Approach 2:
The patent introduces an intermediary error detection circuit that sits between the memory array and the trap registers. This intermediary component detects errors early in the read process and controls when data should be captured in trap registers, eliminating the need for multiple pipeline stages and their associated power consumption.
2Reliability
If trap registers are provided in each memory bank to improve error debugging capability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal error detection circuit that serves multiple memory banks simultaneously. Rather than providing separate trap registers in each bank, the error detection logic operates on read data from any bank and controls a unified trap register structure, reducing overall device complexity while maintaining comprehensive error debugging capability across all banks.
3Speed
If error detection is performed early in the pipeline to improve response time, then speed is improved, but power dissipation increases due to additional logic stages
Solution Approach 1:
The patent segments the error detection function into dedicated logic that operates in parallel with the memory read operation. By separating error detection from the main data path and implementing it as an independent concurrent process, the system achieves fast error detection without adding sequential pipeline stages that would increase power consumption.
Data Source
AI summary
Embodiments include methods, systems and circuits for operating an error trapping logic circuit in a memory device. Aspects include receiving, during a first clock cycle, data and check bits for the data from a memory location and determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits. Aspects also include determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome. Aspects further include determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error.