Latch Layout Interleaving for Multi-Bit Radiation Error Protection
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Solution Overview
Problem
As integrated circuits shrink, they become more susceptible to radiation-induced faults such as single-event upsets (SEUs) and multi-bit upsets (MBUs) due to high-energy particles, which existing protection mechanisms struggle to effectively address.
Innovation Solution
The method involves combining latches into bounding boxes on a circuit design layout based on specific rules and applying a location-aware interleaving of error correction codes (ECC) and burst error correction (BEC) codes to correct multiple bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integrated circuits are shrunk to improve productivity and reduce size, then productivity and compactness are improved, but susceptibility to radiation-induced faults increases
Solution Approach 1:
The patent divides the circuit layout into multiple bounding boxes and applies different error correction strategies to different regions. Latches are segmented into groups that are protected by either ECC or BEC codes based on their location and error risk, allowing differentiated protection without protecting all latches uniformly.
Solution Approach 2:
The patent implements location-aware protection where different error correction mechanisms are applied to different spatial locations. High-risk areas receive BEC code protection while lower-risk areas use ECC codes, optimizing the balance between reliability and resource usage based on local error susceptibility.
2Reliability
If error correction codes are applied to protect latches from radiation faults, then reliability is improved, but device complexity and area increase
Solution Approach 1:
The patent applies error correction codes selectively rather than uniformly to all latches. By identifying and protecting only the most vulnerable latches in bounding boxes with higher error rates, the system achieves adequate protection with fewer correction resources than a comprehensive approach would require.
Solution Approach 2:
The patent changes the error correction parameters dynamically based on location. Different bounding boxes use different error correction codes (ECC vs BEC) and different protection levels, allowing the system to adapt the complexity of protection mechanisms to the actual error risk at each location rather than using a fixed high-complexity approach everywhere.
3Reliability
If comprehensive error correction is applied to all latches, then reliability is improved, but area overhead and resource consumption increase
Solution Approach 1:
The circuit is segmented into multiple bounding boxes with different error correction requirements. By dividing the latches into groups and applying appropriate error correction only where needed, the patent reduces the total area overhead compared to universal protection while maintaining adequate overall reliability.
Solution Approach 2:
The patent applies error correction partially rather than comprehensively to all latches. By focusing protection resources on high-risk bounding boxes and using lighter ECC codes in lower-risk areas, the system achieves acceptable reliability with reduced area overhead compared to full-strength error correction everywhere.
Data Source
AI summary
Embodiments for providing enhanced location-aware protection of latches in a computing environment are provided. One or more latches are combined in one or more of a plurality of bounding boxes on a two-dimensional circuit design layout based on one or more rules. A location-aware interleaving of error correction codes (“ECC”) and burst error correction codes may be selectively applied to one or more latches in those of the plurality of bounding boxes, where multiple bit errors are corrected.