LDPC Parity Mapping for Burst Errors in Defective Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems face challenges due to unreliable storage locations caused by manufacturing defects, which can lead to data corruption and require additional redundancy for error correction, but existing methods do not effectively utilize these defects for improved decoding performance.
Innovation Solution
A memory system that encodes data using information bits, first-type parity bits, and second-type parity bits, where the second-type parity bits are mapped to bad memory cells to enhance decoding performance by utilizing a modified parity-check matrix and Tanner graph structure, allowing for efficient error correction even in unreliable storage locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extra replacement storage locations are configured to deal with unreliable storage locations, then yield is improved, but device complexity increases
Solution Approach 1:
The patent maps second-type parity bits to bad memory cells, converting the harmful effect of defective storage locations into a beneficial resource for error correction. By intentionally placing parity bits in unreliable locations, the system transforms manufacturing defects into functional components that enhance decoding performance without requiring additional replacement storage locations.
2Productivity
If second-type parity bits are mapped to bad memory cells, then decoding performance is improved, but reliability of stored data deteriorates
Solution Approach 1:
Instead of avoiding bad memory cells for parity bit storage, the patent inverts the conventional approach by deliberately mapping second-type parity bits to bad memory cells. This inversion allows the system to exploit the known characteristics of defective locations to improve overall decoding performance while maintaining data integrity through the redundancy provided by parity bits.
3Reliability
If multiple types of parity bits are used, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the parity bit functionality into two distinct types: first-type parity bits for basic error correction and second-type parity bits for enhanced decoding performance. By dividing the error correction function into specialized segments with different roles and mapping strategies, the system achieves improved error correction capability while managing complexity through structured organization of parity bit operations.
Data Source
AI summary
A storage system and method for handling a burst of errors is provided. In one embodiment, the method comprises generating a protograph using an error code generation method; generating a first partially-lifted protograph based on the generated protograph that avoids a first burst of errors; generating a fully-lifted protograph based on the generated protograph and the generated first partially-lifted protograph; and providing the fully-lifted protograph to a storage system comprising a memory.