Memory ECC Layout for Consecutive Bit Error Correction
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Solution Overview
Problem
As integrated circuit manufacturing advances towards greater integration and lower operating voltages, error detection and correction in information processing systems become increasingly important due to rising soft error rates, but existing methods that add storage elements for parity or ECC values increase system size, power consumption, and performance costs.
Innovation Solution
Implementing a new Hamming code for error correction of two consecutive bits and detection of four consecutive bits using 12 check bits, where four check bits are integrated into the main array for detection and eight are moved to an auxiliary structure for correction, reducing area, power, and performance costs, and applying this 'bursty' double-error-correction, quad-error-detection (bDECQED) technique to multiple adjacent bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If storage elements for parity or ECC values are added to information storage structures, then error detection and correction capability is improved, but the size of the storage structure increases
Solution Approach 1:
The patent divides the error correction functionality into two separate storage structures: a main array for data and parity bits, and an auxiliary structure for ECC check bits. This segmentation allows the system to provide comprehensive error detection and correction while optimizing the spatial distribution of storage elements, reducing the impact on overall storage structure size.
Solution Approach 2:
The patent moves eight ECC check bits from the main array to an auxiliary structure, effectively utilizing a second dimension (auxiliary structure) for storage. This dimensional transition allows the system to maintain error correction capability while reducing the area occupied in the primary storage array.
2Reliability
If storage elements for parity or ECC values are added to information storage structures, then error detection and correction capability is improved, but power consumption increases
Solution Approach 1:
By segmenting the storage structures and separating detection (parity bits in main array) from correction (ECC bits in auxiliary structure), the system can optimize power management for each function, potentially reducing overall power consumption compared to a unified approach.
Solution Approach 2:
The patent implements partial error correction by moving only eight ECC check bits to the auxiliary structure while keeping four parity bits in the main array for detection. This partial implementation allows the system to achieve effective error handling while consuming less power than a full correction implementation would require.
3Reliability
If storage elements for parity or ECC values are added to information storage structures, then error detection and correction capability is improved, but performance deteriorates
Solution Approach 1:
The segmentation of error detection and correction functions into separate storage structures allows for optimized access patterns and parallel processing, improving performance by reducing the critical path delay compared to a unified storage structure.
Solution Approach 2:
By implementing a hybrid approach with four parity bits for detection and eight ECC bits for correction distributed across two structures, the system achieves effective error handling with reduced overhead compared to traditional single-structure ECC implementations.
Data Source
AI summary
Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.