LDPC Code Generation Using Trapping Set Cores for Error Floor Verification
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Solution Overview
Problem
Traditional methods for verifying and obtaining low error floors for LDPC codes are inefficient, requiring months or years to achieve error floors lower than 10−6, limiting the reliability of digital communication and storage systems.
Innovation Solution
A method and apparatus that utilize a parity generation circuit, detection circuit, and verification circuit to generate LDPC codes by detecting trapping set cores, performing important sampling simulations, and comparing estimated error floors with an expected error floor, allowing for the output of LDPC codes with required error floors, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verification methods are used to obtain low error floors, then reliability is improved, but the time required increases to months or years
Solution Approach 1:
The patent pre-calculates and stores trapping set core information in a database before the actual verification process. By preparing trapping set patterns and their characteristics in advance, the system avoids performing exhaustive simulations from scratch, thereby significantly reducing the time required to verify error floors while maintaining reliability
Solution Approach 2:
The patent uses important sampling simulation to generate representative error patterns that copy the essential characteristics of rare error events. Instead of simulating all possible error cases, the system creates and analyzes representative samples of trapping set errors, achieving accurate error floor verification in much shorter time
2Measurement precision
If exhaustive simulation is performed to verify error floors lower than 10^-6, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent extracts and focuses only on the critical trapping set patterns that dominate error floor behavior. By identifying and isolating these key trapping set cores from the vast space of all possible error patterns, the system achieves accurate error floor verification without needing to simulate every possible error case, thus maintaining precision while improving productivity
Solution Approach 2:
The patent changes the simulation approach by using important sampling with specifically designed error patterns based on trapping set structures. Instead of uniform random sampling, the system uses parameterized error patterns that target trapping set configurations, achieving both high measurement precision and improved verification speed
Data Source
AI summary
A method for generating an LDPC (low-density parity check) code with a required error floor, comprising: using a parity generation circuit to generate an LDPC code; using a detection circuit to detect the LDPC code according to a plurality of trapping set cores in a database and to generate at least one piece of trapping-set-core information; using a verification circuit to perform an important sampling simulation according to the LDPC code and each trapping-set-core information separately to obtain an estimated error floor for each trapping-set-core information; using the verification circuit to separately compare each of the estimated error floors with an expected error floor; and when all of the estimated error floors are lower than or equal to the expected error floor, using the verification circuit to output the LDPC code.