11T SRAM Cell Structure for Writeability and In-Memory Logic
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Solution Overview
Problem
Existing SRAM devices face challenges such as increased complexity, extra cost, and power consumption due to separate optimization of N-type and P-type transistor effective channel widths, and SRAM-based CIM devices have low computational density due to large area requirements for logic gate operations.
Innovation Solution
Implementing a stacked transistor structure, such as a CFET, with reconfigurable schemes to enhance write ability without additional sizing processes, utilizing previously dummy PFETs for enhanced 11T SRAM cells that perform multiple logic gate functionalities and minimize area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate optimization of N-type and P-type transistor effective channel widths is performed, then write ability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent changes the physical parameter of transistor effective channel width by introducing dummy transistors in series with the write pass transistors. This modifies the effective channel width parameter to improve write ability without requiring separate optimization processes for N-type and P-type transistors, thereby reducing process complexity while maintaining reliability improvement
2Reliability
If write assist technique is introduced, then write ability is improved, but power consumption increases and data stability degrades
Solution Approach 1:
The patent extracts and removes the write assist technique from the SRAM cell design. Instead of using write assist circuits that consume additional power, the invention achieves improved write ability through structural modification of the pass transistors using dummy transistors, thereby eliminating the harmful power consumption effect while maintaining write ability improvement
3Reliability
If write assist technique is introduced, then write ability is improved, but SRAM macro area increases
Solution Approach 1:
The patent merges the dummy transistors with the existing write pass transistor structure, combining multiple functions into a single integrated component. The dummy transistors are merged in series with the write pass transistors to form a unified structure that improves write ability without requiring separate write assist circuits, thereby avoiding additional macro area penalty
4Adaptability or versatility
If SRAM cells and peripheral circuits are used for logic gate operations, then computational functionality is achieved, but area utilization decreases
Solution Approach 1:
The patent applies multi-functionality to the SRAM cell by configuring it to perform both memory storage and logic gate operations. The same SRAM cell structure with modified pass transistors is used universally for both functions, eliminating the need for separate dedicated logic gate circuits and thereby improving area utilization while maintaining computational functionality
Data Source
AI summary
An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.