Logic Circuits Characterised By Logic Function TRIZ Cases

By splitting the division factor into sub-factors and edge-sampling the divider clock, this circuit delivers 50% duty cycle at any ratio.

A stacked 11T SRAM cell boosts low-voltage write ability, avoids half-selected disturb, and adds six CIM logic functions in an 8T-like footprint.

Switching between SRAM and inverter modes helps this reconfigurable PUF deliver more stable, secure responses under noise, voltage, and temperature shifts.

Using oscillator pauses, duty rectification, and synchronized sampling, this case reduces bias and previous-value dependence in random bits.

Bit-line threshold readout enables logic inside non-volatile memory, cutting data-transfer energy while preserving algorithm accuracy.

Mixed-fin flip-flops in one scan-path tray preserve timing closure while cutting IC footprint and power through targeted FinFET sizing.

Selective start-row triggering in cascaded display drivers cuts unnecessary pixel updates, lowering power use and extending standby time.

Active impedance reduction lowers frequency-dependent impedance in clock paths, cutting jitter and noise without large-buffer power penalties.

A stacked CFET-style SRAM cell boosts writeability without write assist and enables six in-memory logic functions with minimal area.

Scan transmission gates replace multiplexers in a multi-bit flip-flop, cutting transistor count, power use, latency, and area.

A capacitor and transmission-gate update path simplify CMOS RPU control while enabling parallel stochastic weight updates for faster neural training.

Large-area TMD flakes grown by molten salt-assisted CVD enable a light-gated transistor with optical logic and fast synaptic response.

Diodes, pull-up resistors, and an isolation barrier replace a CAN transceiver to deliver 8 Mbps microcontroller links with galvanic isolation.

Merging scan selection into the master latch removes extra inversions and multiplexers, cutting transistor count, power use, and delay.

Layered sparse carry-lookahead logic cuts gate count and delay in large bit additions, improving speed, area, and power use.

Selective refresh targets victim rows next to aggressor rows to limit row hammer data loss while cutting unnecessary DRAM power use.

Accumulating match sense signals in page buffer storage elements enables threshold-based in-memory search that tolerates NAND cell defects.

Opposite-edge latching and combinational logic synchronize reset signals with about half-clock latency, reducing channel skew and flip-flop count.

Digitally controlled impedance replaces high-gain preamplifiers in sensor AFEs to cut noise, distortion, and acoustic overload.

Adjusted pull-up and pull-down voltage swings help buffer circuits handle high-frequency clock signals with less jitter and faster output response.

Two inverters replace storage capacitors to hold drive signals, enabling faster writing, lower power use, and scalable droplet arrays.

Separate rising- and falling-edge delays remove short digital pulses while preserving longer signal content and avoiding metastability.

Symmetrical injection stages and frequency calibration cut phase skew and jitter in an injection-locked divider across PVT variation.

Temperature-based masking limits unnecessary DRAM auto refresh pulses, cutting current draw while preserving data integrity.

A thin-oxide CMOS Schmitt trigger uses high-side level shifting to avoid thick-oxide I/O devices, cutting masks, layout overhead, and mismatch.

A VLV GPIO uses dedicated test transmit and receive paths to screen manufacturing defects near core threshold voltage without large area or peak current penalties.

Switching power and ground paths makes NBTI degradation more apparent in a ring oscillator, improving stress-state evaluation and life prediction.

An OR-gated latch detects ring oscillators that remain active after disable, avoiding impractical per-oscillator stuck-at fault testing.

Two-level ECC check codes improve DRAM error detection and correction while simplifying hardware, lowering power use, and speeding encoding.

A continuously connected null-output capacitor stabilizes auto-zero switching, reducing voltage fluctuation, noise, and offset correction errors.

Subthreshold leakage deviation in a cross-coupled bistable PUF cuts transistor count to balance low error rate, stability, and small area.

Test memory cells generate a stable boot-time reference current, improving NVM read accuracy, security, and flexible read modes.

Clock gate controllers extract launch and capture pulses from a reference clock, simplifying multi-domain at-speed IC testing.

A slow idle clock and glitch-mitigation gating balance clock-path aging, preventing duty-cycle distortion and timing violations.

Bulk or gate voltage control adjusts FET charging current to keep spiking neuron pulse timing accurate across process and temperature shifts.

A command-switched transmission path sends latched anti-fuse data to the data port, improving test authenticity by avoiding path inconsistencies.

A looped logic-gate clock circuit doubles 4 input phases to 8 fixed-order outputs, avoiding phase swapping while preserving accuracy at high frequency.

Measures skew between global clock signals from NAND and NOR timing states, enabling delay-line compensation for better chip synchronization.

Separate flip-flops and earlier cross-path signal transfer cut decoder propagation delay and extend command set-up time for faster memory timing.

An OR gate and existing flip-flop expose uncovered combinational logic during scan test, improving coverage without extra observability flops.

A stable clock warms and synchronizes a ring oscillator before free running, improving startup predictability and entropy security.

A reset circuit synchronizes the oscillator phase in a single isolation channel to cut jitter, stabilize transmission, and reduce circuit area and cost.

Dedicated hardware aligns I2S word select and serial clock signals to a network clock reference, cutting jitter and timing uncertainty.

Embedded scan input delay circuitry raises hold time in master-slave flip-flops, reducing clock-skew violations without extra routing.

Widened chip-select pulses mask invalid shared C/A signals before sampling, cutting DRAM power waste and avoiding high-frequency sampling errors.

Differential reading of test cells during NVM boot avoids unstable bandgap current, then enables accurate single-ended reads and secure data access.

An amplitude limiting circuit cuts drive signal amplitude to suppress unwanted quartz vibrations and improve sensor stability and detection accuracy.

Speculative DFE samplers and branch-selected charge pump logic cut clock recovery latency at high data rates while avoiding extra receiver power.

Asynchronous differential charge transfer lets parallel MAC unit elements scale matrix operations while cutting displacement currents and power.

Independent write and read enable control lets latch-based FIFOs achieve ATPG path testing and stuck-at-1 fault detection without losing area savings.

Temporally shifted switch-control edges cut switching resistance in switched-capacitor digital transmitters, improving linearity with lower area and power.

Cycle-complete gating lets clock dividers change frequency, phase, and spread spectrum without glitches, resets, or clock loss.

A lock circuit and level shifter switch between fuse-programming high voltage and a safe intermediate voltage to protect IC components.

A two-stage pre-decoder and single row decoder raise memory row density to 768 or 1024 with lower design effort and area overhead.

NAND-gate duty-cycle sensing and delay adjustment align 45° and 90° clock phases to improve high-speed data recovery accuracy.

By generating the inverted clock internally, this latch cuts idle clock-buffer power while preserving reliable flip-flop operation.

A clock detector disables the correction loop during clock-off periods to prevent error saturation and restore accurate duty-cycle within few cycles.

Multiple pull-up and pull-down paths use inverted signals to speed XOR logic while reducing circuit layout area in semiconductor designs.

Analog multipliers and activation circuits cut memory access and delay, enabling larger neural networks with lower chip power.

Differential wander current sensing corrects SerDes baseline wander with low delay while stabilizing common mode voltage and PSRR.

A modular latch and transmission-gate shift register cuts OLED gate driver cost while supporting efficient forward and backward scanning.

A tree of driving buffers and OR gates routes spikes only to weighted synapse zones, cutting signal-transfer power without losing accuracy.

A comparison and determination circuit detects scan-line shorts and cuts off scan chip output before high-low conduction causes burnout.

Finite DLL bandwidth can cause wraparound glitches; this case shows phase-error correction that keeps clock timing stable during supply droops.

An integrated sense-mixing, redundancy-shift, latch, and level-shift path cuts SRAM read delay and die space while preserving bit transfer reliability.

A cascaded counter circuit generates multiple sampling pulses from one clock while cutting logic count, power use, and layout area.

Proactive hop-code adjustment prevents shortened clock pulses when a digital DLL updates under variable supply conditions.

A NAND-gated bypass and downstream delay layout keeps ring oscillator power constant while frequency is adjusted in ICs.

Programmable delay lines and skew sensing measure control response time while keeping multi-clock domains aligned and reducing data faults.

A self-initialization circuit detects invalid low input pairs during power-up and forces the level shifter output to a known voltage.

By storing non-zero values with a distribution matrix, convolution runs on sparse matrices without zero restoration or invalid calculations.

Fan-in cone analysis and auxiliary code remove false Xs in nested clock gater chains, improving gate-level simulation accuracy.

Compensation capacitance balances inverter-path delays to cut complementary-signal skew and PVT variation at higher operating frequencies.

External shorting pins inhibit data destruction during authorized maintenance, while backup power keeps tamper response active after main power loss.

Digital counters switch resistive circuits to store ANN weights, reducing variability, symmetric update errors, and power loss.

A gated ring oscillator and counting scheme extends TDC phase range and removes dead zones while reducing area and power.

A feedback-controlled spread-spectrum clock keeps transmitter and receiver timing aligned, cutting EMI without sacrificing high-data-rate transmission.

Combining smoke and temperature sampling with threshold logic cuts false alarms while preserving fire detection capability.

A modified Muller C-element waits for both differential lines to switch, preventing premature high-voltage output glitches.

Pre-emphasis control boosts memory output driver strength for faster signal transitions without simply enlarging the driver structure.

Adjacent-bit thermometer code correction protects coarse DLL delay lines from multiple bit flips without slowing high-speed clock synchronization.

A latch stores the control signal before it floats, while clamp isolation cuts leakage and prevents bad delay-line propagation during wake-up.

Independent delay stages and unit current control let rising and falling edges be tuned separately to cut EMI without overcomplicating the circuit.

Conservative reversible logic with extended flip-flops and Fredkin gates detects BTI-related timing faults with two self-test vectors.

By delaying one pulse edge before inversion, this circuit preserves pulse width and duty cycle while simplifying slope-controlled signal transmission.

A shared multiplex drive module switches between D-PHY and C-PHY outputs to cut interface circuit cost without separate drivers.

A rising bias current is stopped by amplitude feedback, helping crystal oscillators start across resistance spread without parasitic oscillations.

Multiple control terminals let the same function be triggered through alternate key paths, keeping an electronic device usable when a key fails.

Programmable rise and fall current shaping with feedback cuts RF-band harmonics from SoC I/O pads, reducing magnetic coupling to nearby RF circuits.

Bias current reversal at voltage thresholds lets a memristor oscillator self-adjust resistance for more flexible frequency control.

Weak pull-down transistors let output stabilization start before feedback goes high, cutting clock-to-output delay in SOC latches.

Dual detecting circuits and OR gating identify I3C start and stop patterns early enough to give slave devices safe latching time.

Adjusted pull-up and pull-down slew rates reduce amplitude attenuation and signal distortion in high-speed memory data transmission.

A boosted gate driver uses a higher on-chip supply to widen NAND SSL on/off margin, reducing charge leakage during self-boosting.

A 5-transistor cascaded latch generates stable multi-phase signals with lower power, reduced jitter, and higher-frequency operation.

Reusing SPI or SWD interface terminals lets an input circuit generate chip reset signals without dedicated reset pins or internal POR.

Dual delay paths and a multiplexer preserve clock duty cycle while reducing distortion and supply-ground disturbances across PVT variation.

Aligned delay clocks and synchronous data cut parasitic load and transistor depth, enabling faster high-bandwidth serialization.

Stored-key checks let a memory controller verify access commands and update data lines with protective patterns when access is unauthorized.

A wider-swing drive signal boosts pull-up transistor current, shortening leakage periods and speeding voltage level shifting with less area penalty.