Reset Synchronizer Circuit for Low-Latency Metastability Blocking
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Solution Overview
Problem
High-speed communications networks face issues with inter-channel data skew due to metastability conditions in reset synchronization circuits, leading to unsynchronized reset control signals and increased recovery time, which can result in data skew between channels.
Innovation Solution
A reset synchronization circuit comprising a first and second latching circuit configured to respond to opposite edges of a clock signal, combined using combinatorial logic to generate a logic output signal, and a third latching circuit to produce a synchronization control signal, reducing the number of flip-flop circuits and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple flip-flop circuits are serially connected to block metastability conditions, then reliability is improved, but device complexity and latency increase
Solution Approach 1:
The patent combines the metastability blocking function with the reset synchronization function into a single integrated circuit. The reset synchronization circuit generates synchronized reset signals for multiple serializer circuits while simultaneously blocking metastability conditions, eliminating the need for separate blocking circuits and reducing overall device complexity
Solution Approach 2:
The reset synchronization circuit performs multiple functions: it synchronizes reset signals across multiple channels, blocks metastability conditions, and provides controlled reset timing. This multi-functional approach replaces what would traditionally require multiple separate circuits, reducing both complexity and component count
2Reliability
If multiple flip-flop circuits are serially connected to block metastability conditions, then reliability is improved, but recovery time increases beyond single clock cycle
Solution Approach 1:
The circuit uses preliminary action by capturing the reset signal state at predetermined clock edges before it can cause metastability issues. The flip-flops are configured to latch the reset signal at specific clock transitions, ensuring that reset assertions are synchronized to clock edges and metastability conditions are blocked in advance
Solution Approach 2:
The patent rushes through the metastability blocking process by using a streamlined circuit configuration that resolves reset synchronization in a single clock cycle. The direct connection of flip-flop outputs to serializer reset inputs, combined with careful timing configuration, allows the circuit to skip intermediate delay stages and achieve synchronization quickly
3Loss of time
If reset control signals are not synchronized to clock edge, then latency is reduced, but inter-channel data skew occurs
Solution Approach 1:
The circuit uses feedback by monitoring the clock signal edges and using them to control the timing of reset signal assertions. The flip-flops are clocked by the system clock, and their outputs are generated in synchronization with clock edges, creating a feedback mechanism that ensures precise timing alignment across all channels without adding significant latency
Data Source
AI summary
A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.