Gated Ring Oscillator Topology for Constant Power Across Frequency Tuning
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Solution Overview
Problem
Existing pure digital gated ring oscillator designs experience variations in power consumption as oscillation frequency is adjusted, leading to performance degradation and complexity in internal power rail designs within integrated circuits.
Innovation Solution
A ring oscillator circuit topology with constant power consumption is achieved by positioning delay elements downstream of a path selector and using multiplexers with NAND gates, where transistors in the delay element do not toggle when the non-delaying signal path is selected, ensuring a proportional relationship between total capacitance and oscillation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If frequency is adjusted in pure digital gated ring oscillator, then oscillation frequency changes, but power consumption varies
Solution Approach 1:
The patent applies dynamics by making the delay element configuration adjustable through a control signal. When the control signal is high, delay elements are included in the oscillation path to reduce frequency; when low, they are excluded to increase frequency. This dynamic reconfiguration allows frequency adjustment while maintaining constant power consumption because the same number of inverters remain active throughout operation.
Solution Approach 2:
The patent segments the ring oscillator into two distinct paths: an oscillation path containing a selective number of inverters, and a bypass path containing additional delay elements. This segmentation allows the delay elements to be selectively included or excluded from the oscillation path without affecting the active inverter count, thereby enabling frequency control while maintaining constant power consumption.
2Speed
If delay elements are added to adjust frequency, then oscillation frequency decreases, but power consumption increases
Solution Approach 1:
The control signal dynamically switches the configuration of delay elements between two states: included in the oscillation path or bypassed. This dynamic switching allows the circuit to adjust frequency by changing the number of active delay elements in the oscillation loop, while the total number of active inverters remains constant, preventing power consumption increase.
Solution Approach 2:
The patent extracts the delay function from the main oscillation path by providing a separate bypass path. This allows delay elements to be removed from active participation in oscillation when frequency increase is desired, without removing them from the circuit entirely. The bypass path enables selective extraction of delay elements from the critical oscillation loop, controlling frequency while maintaining constant power consumption.
Data Source
AI summary
A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.