Scan Flip-Flop Input Delay for Hold Time Compliance
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Solution Overview
Problem
Synchronous circuits in semiconductor devices often experience hold time violations due to clock skew, which existing technologies struggle to address effectively, particularly in scan flip-flop circuits used for testing, leading to timing violations and operational issues.
Innovation Solution
The implementation of scan input circuitry within the flip-flop that introduces a delay in the scan input signal path, using a combination of buffers and logic gates to generate a delayed scan input signal, allowing for improved hold time by managing clock signals and enabling effective scan testing modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan input circuitry with delay is added to the flip-flop, then hold time violations are mitigated and operational stability is enhanced, but device complexity increases
Solution Approach 1:
The scan input delay circuitry is nested within the flip-flop structure itself, specifically integrated into the master latch. The delay logic is embedded between the scan input and the master latch input, allowing the delay function to be contained within the existing flip-flop boundaries without requiring external routing resources.
Solution Approach 2:
Additional logic gates are introduced as intermediary elements between the scan input signal and the master latch. These intermediary gates provide the necessary delay functionality while maintaining signal integrity and enabling hold time compliance without directly modifying the core latch structure.
2Reliability
If delay is introduced in scan input signal path, then hold time is improved, but signal propagation time increases
Solution Approach 1:
The delay is applied locally and selectively only to the scan input signal path, not to all inputs of the flip-flop. The normal data input path remains unaffected, ensuring that functional operation timing is preserved while only the scan path experiences the additional delay needed for hold time compliance.
Solution Approach 2:
The scan input delay circuitry is controlled dynamically through the scan enable signal. When scan mode is active, the delay logic is enabled; when functional mode is active, the delay is bypassed. This dynamic control allows the system to adapt its timing characteristics based on operational mode.
Data Source
AI summary
Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.