Multi-Bit Flip-Flop Scan Chain With Reduced Transistor Count
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Solution Overview
Problem
Existing multi-bit flip-flops require a significant number of transistors, failing to achieve power and area savings in complex digital systems.
Innovation Solution
A multi-bit flip-flop circuit design with reduced transistor count, utilizing input sub-circuits, primary and secondary latch sub-circuits, and output inverters, along with scan transmission gates instead of multiplexers, to minimize transistor usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If existing multi-bit flip-flop architectures are used to reduce design area, then area is reduced relative to single-bit flip-flops, but the number of transistors remains significant leading to failed power savings
Solution Approach 1:
The flip-flop is divided into two independent sub-circuits (first and second flip-flop sub-circuits), each capable of storing one bit. This segmentation allows the multi-bit flip-flop to achieve area reduction while minimizing transistor count by using shared clocking infrastructure rather than duplicating complete flip-flop structures.
Solution Approach 2:
The shared clock signal and clock distribution network serve multiple functions: they control both sub-circuits simultaneously, enable scan testing across both bits, and provide timing synchronization. This multi-functionality reduces the overall transistor count while maintaining area efficiency.
2Area of stationary object
If multi-bit flip-flops are used to store multiple bit signals with a single clock signal, then area is saved, but the complexity of the flip-flop architecture increases
Solution Approach 1:
By segmenting the multi-bit flip-flop into independent sub-circuits with identical structures, the design achieves area efficiency while managing complexity through modularity. Each sub-circuit can be designed and verified independently, then combined using shared clocking resources.
3Reliability
If scan chain testing is implemented in multi-bit flip-flops, then testing capability is improved, but the number of transistors increases
Solution Approach 1:
The clock signal and distribution network serve dual purposes: normal operational timing and scan chain testing control. This multi-functionality allows scan testing capability to be achieved without adding dedicated testing transistors, as the existing clock infrastructure is repurposed for testing operations.
Data Source
AI summary
Embodiments disclosed herein relate to device testing using scan chains including various flip-flop devices in a multi-bit flip-flop configuration. A circuit device included herein includes a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit is coupled to receive a clock signal and an input, and the second flip-flop circuit is coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub-circuit, a first latch sub-circuit, a first latch tristate, a second latch sub-circuit, and a first output inverter. The second latch sub-circuit includes a first transmission gate, a first inverter, and a second inverter. The second flip-flop sub-circuit includes a second transmission gate, a first clock tristate, a third latch sub-circuit, a second latch tristate, a fourth latch sub-circuit, and a second output inverter. The fourth latch sub-circuit includes a third transmission gate, a third inverter, and a fourth inverter.