DLL Clock Stretcher Glitch Correction Under Supply Voltage Droop
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Solution Overview
Problem
Conventional clock stretchers require a clean power supply and struggle with glitches due to finite DLL bandwidth and phase detector offset, especially in systems with variable load conditions, leading to timing violations and functional failures.
Innovation Solution
A clock stretcher system that includes a sense unit, a delay-locked loop (DLL), and a combiner, which senses supply voltage changes and adjusts the clock frequency by cyclically selecting delayed phases to generate a modified clock, correcting for DLL phase errors and phase detector offsets without the need for a clean power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a DLL feedback loop is designed with limited bandwidth to ensure stability, then the system stability is improved, but the DLL cannot keep up with fast supply voltage changes, causing timing violations
Solution Approach 1:
The patent applies preliminary action by proactively detecting supply voltage droops before they cause timing violations and pre-adjusting the clock pulse width. The voltage droop detector monitors supply voltage in real-time and triggers clock stretching before the voltage drop affects clock timing, preventing timing violations rather than correcting them after they occur.
Solution Approach 2:
The patent implements feedback by using the voltage droop detector to continuously monitor supply voltage and dynamically adjust the clock signal parameters based on detected voltage conditions. The system measures the actual voltage state and feeds this information back to the clock stretcher control logic, which then modifies the output clock accordingly to maintain timing integrity.
2Manufacturing precision
If the delay line resolution is increased to improve clock frequency precision, then the manufacturing precision is improved, but the power consumption and die area increase
Solution Approach 1:
The patent applies dynamics by making the delay line resolution adaptive rather than fixed. The system dynamically adjusts the effective delay line resolution based on the detected supply voltage conditions and timing requirements. When voltage is stable, lower resolution suffices; when voltage droops are detected, the system increases effective resolution by making finer adjustments to clock pulse stretching, thereby achieving high precision only when necessary.
Solution Approach 2:
The patent implements parameter changes by dynamically modifying the delay line control parameters based on supply voltage conditions. The system changes the effective delay values and resolution settings in real-time according to the monitored voltage state, allowing the delay line to operate at optimal precision levels that match the actual timing requirements rather than maintaining maximum resolution continuously.
3Ease of operation
If a digital DLL is used to eliminate the need for a clean power supply, then the ease of operation is improved, but glitches occur at the time of DLL adjustment, causing timing violations
Solution Approach 1:
The patent applies preliminary anti-action by detecting supply voltage droops that would cause digital DLL adjustment glitches and proactively stretching the clock pulse before the glitch occurs. The voltage droop detector identifies the harmful voltage condition and triggers a compensatory clock stretch that prevents the timing violation caused by the upcoming DLL reconfiguration, counteracting the potential harm before it manifests.
Solution Approach 2:
The patent implements beforehand cushioning by extending the clock pulse width in advance of anticipated DLL adjustments triggered by voltage droops. This creates a timing buffer or cushion that absorbs the disruptive effect of the DLL reconfiguration, ensuring that the extended pulse duration covers the glitch period and maintains valid timing for downstream logic.
4Productivity
If the clock frequency is increased to improve processing speed, then the productivity is improved, but timing violations occur when supply voltage droops
Solution Approach 1:
The patent applies dynamics by making the clock frequency adaptive rather than fixed. The system dynamically adjusts the output clock frequency and pulse width based on real-time supply voltage conditions. When voltage is nominal, the system operates at maximum frequency for high productivity; when voltage droops are detected, the system automatically reduces frequency and extends pulse widths to maintain timing integrity, creating a dynamic balance between speed and reliability.
Solution Approach 2:
The patent implements feedback by using supply voltage monitoring to continuously adjust clock frequency parameters. The voltage droop detector provides real-time feedback about power supply conditions, and the control logic uses this feedback to modulate the clock signal characteristics, reducing frequency when voltage drops and restoring it when voltage stabilizes, thereby preventing timing violations while maximizing productivity during stable operation.
Data Source
AI summary
A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The DLL has a phase error because of its finite bandwidth. The clock stretcher measures the phase error and corrects for a glitch in the modified clock signal by using the phase error when phase selection wraparound occurs. The clock stretcher may operate from a power supply that has droops, without intervening voltage regulation.