DRAM ECC Encoding with Byte- and Bit-Level Check Codes
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Solution Overview
Problem
As semiconductor memory technologies advance and memory density increases, errors in Dynamic Random Access Memory (DRAM) storage become more prevalent, necessitating effective error detection and correction mechanisms to maintain performance.
Innovation Solution
A memory system that divides data into bytes and generates both first and second check codes using parity check principles, where the first check codes are configured for error detection or correction on individual bits within bytes, and the second check codes are configured for error detection or correction on entire bytes, reducing hardware complexity and power consumption while optimizing ECC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC techniques are used to detect or correct errors in high-density DRAM, then error detection and correction capability is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent divides data into multiple bytes and generates two types of check codes: first check codes for individual bytes and second check codes for groups of bytes. This segmentation allows the ECC system to handle errors at different granularities, reducing the overall hardware complexity compared to traditional monolithic ECC approaches while maintaining comprehensive error detection and correction capability.
Solution Approach 2:
The patent applies check codes selectively based on error patterns. Second check codes are generated only for groups of bytes when needed, rather than applying full ECC to every byte unconditionally. This partial action approach reduces hardware complexity and power consumption while maintaining adequate error protection for high-density DRAM.
2Reliability
If traditional ECC techniques are used to detect or correct errors in high-density DRAM, then error detection and correction capability is improved, but power consumption increases
Solution Approach 1:
By segmenting the ECC process into first check codes for individual bytes and second check codes for byte groups, the patent enables more efficient power management. The segmented approach allows the system to activate only the necessary check code generation circuits based on the specific error conditions, reducing overall power consumption compared to continuously operating full ECC circuits.
Solution Approach 2:
The patent changes the parameter of check code granularity by introducing two different levels of check codes (byte-level and group-level). This parameter change enables the system to adapt power consumption to the actual error conditions, consuming less power when full ECC is not needed while maintaining reliability when errors occur.
3Reliability
If comprehensive ECC is applied to all data, then error detection and correction coverage is improved, but encoding speed decreases
Solution Approach 1:
The patent segments the encoding process into parallel operations: first check codes are generated for each byte independently while second check codes are generated for groups of bytes. This segmentation enables parallel processing that maintains comprehensive error coverage while improving encoding speed compared to sequential comprehensive ECC approaches.
Data Source
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AI summary
Embodiments of the disclosure provide a memory system including: a memory, configured to, during a read or write operation, write or read multiple data, here the multiple data are divided into M bytes, each having N data; and an encoding module, configured to generate, at an encoding stage, X first check codes, each based on a subset of the data at fixed bits among all the bytes, and to generate, at the encoding stage, Y second check codes based on all data in a subset of the bytes, here the X first check codes are configured for at least one of error detection or error correction on the N data in each of the bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes. The embodiments of the disclosure facilitate performance of the memory system to be improved.