Differential Level Shifter Combiner for Glitch-Free Output
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Solution Overview
Problem
Level shifters that convert binary signals from a low-voltage domain to a high-voltage domain often experience glitches due to fast common-mode slew rates and failure of complementarity in differential signals, leading to premature transitions in the single-ended output.
Innovation Solution
A translation circuit using a two-input Muller C-element circuit with one inverted input, implemented with NAND gates and inverters, is employed to ensure that the output changes state only after both elements of the differential signal have inverted, thereby eliminating glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a differential signal is used to achieve low propagation delay and high slew rate, then propagation delay is reduced and slew rate is improved, but glitches occur due to fast common-mode slew rate and failure of complementarity
Solution Approach 1:
A Muller C-element circuit is introduced as an intermediary between the differential signal and the single-ended output. This mediator synchronizes the transitions of both differential signal lines and ensures that the output changes state only when both inputs are valid, thereby eliminating glitches caused by incomplete complementarity while maintaining fast response characteristics
Solution Approach 2:
The Muller C-element performs preliminary validation of the differential signal complementarity before allowing the output to transition. By checking both signal lines and ensuring they are in valid states before changing the output, the circuit prevents premature transitions and eliminates glitches while preserving fast slew rate
2Speed
If a differential signal is used to achieve low propagation delay, then propagation delay is minimized, but glitches occur due to fast common-mode slew rate
Solution Approach 1:
The fast common-mode slew rate, which causes glitches, is converted into a benefit by using it to quickly establish valid signal states. The Muller C-element leverages the fast transitions to rapidly validate both differential lines and produce a clean, glitch-free output transition, transforming the harmful effect into a useful feature
Solution Approach 2:
The Muller C-element acts as a mediator that filters out the harmful glitch effects of fast common-mode slew rate while preserving the beneficial fast transition characteristics. It synchronizes the output transition with the completion of both differential signal transitions, eliminating glitches
3Device complexity
If a simple combiner circuit is used to convert differential signal to single-ended output, then device complexity is reduced, but glitches occur due to failure of complementarity
Solution Approach 1:
A Muller C-element circuit is introduced as an intermediary between the differential signal and the single-ended output. This mediator synchronizes the transitions of both differential signal lines and ensures that the output changes state only when both inputs are valid, thereby eliminating glitches caused by incomplete complementarity while maintaining fast response characteristics
Solution Approach 2:
The Muller C-element inherently provides feedback by maintaining its output state until both inputs are valid. This feedback mechanism ensures that the output only transitions when the differential signal complementarity is properly established, preventing glitches without requiring complex additional circuitry
Data Source
AI summary
A level shifter comprising: a translation circuit having two input lines and two output lines and configured to receive a differential signal in a low-voltage domain on the two input lines and provide a second differential signal, being a copy of the first differential signal, in a high-voltage domain on the two output lines; and a combiner circuit configured to convert the second differential signal into a single-ended signal at a high-voltage shifter output; wherein the combiner circuit comprises a two-input Muller C-element circuit wherein one input is inverted. Corresponding methods are also disclosed.