Clock Recovery Logic and Charge Pump for Low-Latency Speculative DFE
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Solution Overview
Problem
High-speed communications systems face challenges in achieving low latency and high data communication rates due to extraneous protocol transitions and the inability to calculate Decision Feedback Equalization (DFE) compensation in time at higher data rates, leading to increased receiver power utilization and complexity.
Innovation Solution
A multi-phase speculative DFE system that generates multiple data detection samplers with distinct speculative DFE compensation values, allowing for timely data detection and clock recovery by analyzing transitional data patterns and error signals to adjust the sampling clock, thereby reducing latency and improving PLL loop bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If receive sampling is performed at higher than transmitted data rate to enable clock recovery, then clock data recovery capability is improved, but receiver power utilization increases
Solution Approach 1:
The patent applies preliminary action by performing speculative DFE computations in advance for multiple potential data bit values before the actual data is received. Multiple data detection samplers are prepared with pre-calculated speculative compensation values, allowing the system to quickly select the correct sampler based on the actual received data, thereby enabling timely clock recovery without requiring continuous high-rate sampling.
2Measurement precision
If DFE compensation is calculated using known previous data values at higher data rates, then measurement precision is improved, but detection and computation time increases latency
Solution Approach 1:
The system performs speculative DFE computations in advance for multiple potential data bit values (0 and 1) before the actual data is received. Multiple data detection samplers are prepared with pre-calculated speculative compensation values, allowing the system to quickly select the correct sampler based on the actual received data, thereby enabling timely clock recovery without requiring continuous high-rate sampling.
Solution Approach 2:
The patent implements a dynamic selection mechanism where multiple data detection samplers with different speculative DFE compensation values are maintained, and the appropriate sampler is dynamically selected based on the actual received data. This allows the system to adapt to different data scenarios in real-time, achieving both high precision and low latency.
3Loss of time
If multiple data detection samplers with speculative DFE compensation values are used, then data detection timeliness is improved, but device complexity increases
Solution Approach 1:
The patent segments the DFE computation function into multiple parallel data detection samplers, each handling a specific speculative data bit value. This segmentation allows simultaneous processing of multiple possibilities, reducing detection latency. The charge pump circuit is also segmented into multiple branches, with each branch corresponding to a specific transitional data pattern, enabling parallel processing of different scenarios.
Solution Approach 2:
The patent merges the logic network and charge pump circuit into a unified structure where the charge pump branches are directly controlled by logic expressions evaluating transitional data patterns. This integration reduces the number of discrete components and simplifies the control architecture, thereby reducing device complexity while maintaining the benefits of multiple speculative paths.
4Reliability
If extraneous communications protocol transitions are introduced to facilitate clock recovery, then clock signal extraction is improved, but achievable data communication rate is limited
Solution Approach 1:
The patent extracts clock information directly from the data transitions themselves rather than relying on extraneous protocol transitions. By using DFE compensation to predict and compensate for ISI effects, the system can accurately detect data transitions and extract clock signals from the actual data stream, eliminating the need for additional protocol overhead and thereby increasing achievable data communication rates.
Data Source
AI summary
Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.