Very Low Voltage GPIO Circuit for Defect Screening
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Solution Overview
Problem
Conventional defect screening methods for low voltage integrated circuit devices face challenges in identifying defects at very low core supply voltages without requiring large circuit areas or high peak currents, limiting their effectiveness in detecting manufacturing defects.
Innovation Solution
A very low voltage (VLV) input/output (I/O) circuit and method that includes a general-purpose GPIO circuit capable of operating in both functional and low core-Vdd optimized test modes, using a VLV transmitter and receiver connected over a main output stage to communicate with a single I/O pad, allowing for defect screening at voltages close to the threshold voltage of Core FETs, thereby minimizing overvoltage violations and enabling efficient defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard level shifters are used for defect screening at low voltage, then I/O interface functionality is achieved, but circuit area increases and peak currents become excessively high
Solution Approach 1:
The patent changes the operating voltage parameter from standard low voltage levels to very low voltage (VLV) operation close to the threshold voltage Vth of core transistors. This parameter change enables defect screening functionality while reducing the overdrive voltage available to level shifters, thereby preventing excessive area growth and peak current consumption that would occur with standard level shifter designs operating close to Vth.
Solution Approach 2:
The patent segments the I/O circuit into separate VLV-optimized transmitter and receiver paths that operate independently from standard I/O level shifters. This segmentation allows defect screening to proceed through dedicated VLV test mode circuits that bypass the area-consuming and high-current standard level shifter architecture, achieving reliable defect detection without the associated area and current penalties.
2Adaptability or versatility
If I/O level shifters operate close to threshold voltage Vth to achieve low voltage operation, then voltage compatibility is improved, but circuit area and peak currents increase significantly
Solution Approach 1:
The patent changes the voltage operating point to very low voltage (VLV) close to threshold voltage Vth, which improves voltage compatibility for low-power operation. However, it specifically designs VLV-optimized transmitter and receiver circuits that operate in this regime without requiring standard level shifters, thereby avoiding the exponential increase in peak current that would result from forcing standard level shifters to operate close to Vth.
3Measurement precision
If conventional defect screening is performed at higher voltages, then defect detection capability is maintained, but very low voltage operation requirements cannot be met
Solution Approach 1:
The patent implements dynamic voltage adaptability by creating I/O circuits that can operate in multiple voltage regimes: standard low voltage for normal operation and very low voltage (VLV) close to Vth for defect screening. The circuit dynamically adapts to the required voltage range through test mode control signals that enable VLV-optimized transmitter and receiver paths, maintaining defect detection capability while meeting very low voltage operation requirements that conventional fixed-voltage circuits cannot satisfy.
Data Source
AI summary
A GPIO includes a transmitter having an output stage connected to the I/O pad and adapted to supply transmit data to an I/O pad in response to output data generated by a low voltage core logic operating within a functional voltage range for transmit operations; a receiver adapted to supply receive data to the low voltage core logic operating within the functional voltage range in response to input data received at the I/O pad for receive operations; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter and not directly to the I/O pad in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core supply voltage range in response to input data received from the output stage of the transmitter.