Scan Chain OR-Gate Observation for Uncovered Logic Coverage
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Solution Overview
Problem
Conventional scan-design techniques fail to achieve 100% coverage in testing digital circuits, leading to uncovered functional combination logic, which requires additional components like observability flip-flops or expensive software simulation tools, resulting in increased cost, time, and circuit delay.
Innovation Solution
A digital circuit configuration that includes an OR gate and a flip-flop, where the OR gate's input is coupled to a control signal to test uncovered functional combination logic, and the flip-flop's output is observed to detect defects, eliminating the need for observability flip-flops and reducing test time and cost by using existing flip-flops and generating control signals internally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional scan-design techniques are used, then the digital circuit can be tested, but scan coverage is incomplete (less than 100%) for functional combination logic
Solution Approach 1:
An OR gate is introduced as an intermediary component between the uncovered functional combination logic and the scan chain. The OR gate combines the output of the uncovered logic with a control signal, allowing the scan chain to observe the output of the previously uncovered functional combination logic through the scan chain without adding complex observability flip-flops
2Reliability
If observability flip-flops are added to the scan chain to improve coverage, then scan coverage increases, but circuit delay and cost increase
Solution Approach 1:
Existing flip-flops in the scan chain are utilized to serve dual purposes: their normal function and the additional function of observing uncovered functional combination logic. The existing flip-flops capture and hold the combined signal from the OR gate, allowing observation of uncovered logic outputs without requiring additional observability flip-flops, thereby avoiding increased circuit delay
3Reliability
If observability flip-flops are added to achieve complete coverage, then scan coverage improves, but the number of components and cost increase
Solution Approach 1:
The OR gate is designed to perform multiple functions: it combines the control signal with the output of uncovered functional combination logic, and its output is fed to existing scan chain flip-flops that already exist for other purposes. This multi-functional approach allows complete coverage without adding observability flip-flops, as the existing flip-flops serve both their original function and the new observation function
4Reliability
If expensive software simulation tools are used to test uncovered logic, then coverage improves, but test time and cost increase
Solution Approach 1:
The patent replaces the need for expensive software simulation tools with a hardware-based solution. The OR gate and existing scan chain flip-flops provide direct hardware observation of uncovered functional combination logic outputs, eliminating the need for external software simulation and significantly reducing test time and cost
Data Source
AI summary
According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.