Flip-Flop Circuit With Integrated Scan Selection and Lower Transistor Count

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Flip-flop circuits face challenges in achieving faster operation, reduced power consumption, and smaller footprint due to signal inversions and the need for additional components like multiplexers and transmission gates.

Innovation Solution

The flip-flop circuit design reduces signal inversions by merging or replacing the scan multiplexer, utilizing symmetric cross-coupled Or-And-Inverter (OAI) and And-Or-Inverter (AOI) logic gates, and eliminating the need for a conventional multiplexer, thereby reducing transistor count and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional multiplexer and transmission gates are used in flip-flop circuits, then data selection and signal routing are achieved, but device complexity and transistor count increase

Engineering Contradiction:

Improvedata selection capabilityVSAvoidtransistor count

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the scan multiplexer functionality directly into the master latch circuit by using the clock signal and its complement to control data selection. The transmission gate is integrated with the latch transistors rather than being a separate component, reducing overall transistor count while maintaining data selection capability between scan and normal modes.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The clock signal serves multiple functions: it controls the master latch operation, enables data selection between scan and normal modes, and drives the overall flip-flop timing. This multi-functionality eliminates the need for dedicated multiplexer control signals and reduces component count.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If additional components like multiplexers and transmission gates are added to flip-flop circuits, then signal routing flexibility is improved, but power consumption increases

Engineering Contradiction:

Improvesignal routing flexibilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent combines the transmission gate functionality with the master latch transistors, eliminating separate transmission gate components. The scan multiplexer is merged into the latch structure, reducing the number of active components that consume dynamic power during operation.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts and eliminates unnecessary signal inversion stages from the conventional flip-flop design. By using direct coupling between the master and slave latches through cross-coupled feedback, the design removes redundant inverting buffers that would otherwise consume additional power.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If more components are used in flip-flop circuits, then reliability and functionality are improved, but fabrication area increases

Engineering Contradiction:

Improvecircuit functionalityVSAvoidfabrication area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple functions into shared circuit elements: the transmission gate shares transistors with the master latch, the clock signal controls both latch operation and mode selection, and cross-coupled feedback paths serve both latching and data selection functions. This integration significantly reduces the total fabrication area while maintaining reliability.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If signal inversions are performed in flip-flop circuits, then logic level control is achieved, but speed performance deteriorates

Engineering Contradiction:

Improvelogic level controlVSAvoidcircuit operation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent removes unnecessary signal inversion stages from the conventional flip-flop design. By using direct coupling and cross-coupled feedback between master and slave latches, the design maintains proper logic level control while eliminating redundant inverting buffers that add propagation delay.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12407336B2Flip flop circuit

Publication Date: 2025.09.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A flip flop circuit includes a first master portion, a second master portion, at least one determining portion and a slave portion. The first master portion is configured to operate at a first mode and to receive a first input and generate first master outputs. The second master portion is configured to operate at a second mode and to receive a second input and generate second master outputs. The at least one determining portion is configured to receive at least one enable signal, and has determining inputs and determining outputs. The determining inputs are connected to the first master outputs and the second master outputs. The determining portion is configured to determine the determining outputs being the first master outputs or the second master outputs according to the at least one enable signal. The slave portion is configured to receive the determining outputs and generate an output signal.