In-Memory Logic Circuit Using Bit-Line Threshold Readout

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Solution Overview

Problem

Existing in-memory computing circuits face challenges such as increased surface area, complexity, and energy consumption due to data transfer between memory and computing units, and accuracy issues in executing complex algorithms.

Innovation Solution

A data storage circuit with a non-volatile memory array and processing circuit that performs logic operations within the storage circuit, using variable electric biasing ferroelectric or resistive memory cells, allowing parallel data processing and reducing energy consumption by integrating rewrite operations without data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If data is transferred between memory circuits and computing circuits, then computing operations can be performed, but energy consumption increases and computing speed decreases

Engineering Contradiction:
Improveenergy consumptionVSAvoidcomputing speed
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent merges memory storage and computing functions into a single integrated circuit. Memory cells store data while embedded logic circuits perform computations directly on the stored data, eliminating the need for data transfer between separate memory and computing units. This integration simultaneously reduces energy consumption and improves computing speed.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If supplementary transistors are added to each memory cell to enable logic processing, then in-memory computing capability is achieved, but surface area increases and manufacturing costs rise

Engineering Contradiction:
Improvelogic processing capabilityVSAvoidsurface area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent makes memory cells multi-functional by enabling them to perform both storage and computing operations. The same memory cell structure that stores data also contains embedded logic circuits that can perform logical operations directly on the stored data, eliminating the need for additional dedicated computing components and reducing overall surface area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The memory cells are designed to be self-sufficient by incorporating logic processing capabilities within each cell. The memory cells can perform logical operations on their own stored data without requiring external computing resources, enabling in-memory computing while minimizing the need for additional circuitry and reducing surface area.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If complex algorithms are executed using conventional architecture with separate memory and computing units, then computational tasks can be performed, but energy loss during data transfer reaches up to 90%

Engineering Contradiction:
Improvealgorithm execution capabilityVSAvoidenergy loss during data transfer
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent combines memory storage and algorithm execution into a single integrated unit. Memory cells contain embedded logic circuits that enable direct execution of computational algorithms on stored data without requiring data to be transferred to separate computing units, thereby eliminating the 90% energy loss associated with data transfer in conventional architectures.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12437792B2Data logic processing circuit integrated in a data storage circuit
Publication Date: 2025.10.07 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
  • US12437792B2 patent drawing
  • US12437792B2 patent drawing
  • US12437792B2 patent drawing

AI summary

A data storage circuit includes an array of memory cells; a logic processing circuit configured to carry out a logic operation having N binary data as operands stored in N input memory cells, with N≥2, the second input/output nodes of the input memory cells being linked by a common bit line, the logic processing circuit comprising: a transimpedance amplifier stage configured to supply an analogue read signal from the voltage of the common bit line; a comparator intended to compare the analogue read signal with a first adjustable reference voltage in order to generate a digital output signal corresponding to the result of the logic operation; a control unit configured to adjust the reference voltage to an amplitude selected from among N distinct predetermined amplitudes, depending on the type of logic operation.