Clock Gate Control for Multi-Domain At-Speed IC Testing
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Solution Overview
Problem
Conventional integrated circuit (IC) testing methods require complex clock management and additional components for generating launch and capture pulses during at-speed testing, leading to increased size and design complexity, especially for multi-domain testing.
Innovation Solution
A clocking system with multiple clock gate controllers and clock gates that generate enable signals to extract launch and capture pulses directly from a reference clock signal, eliminating the need for dividers and chopping circuits, and allowing for simpler design and implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional clock management with dividers and chopping circuits is used to generate launch and capture pulses, then accurate at-speed testing can be achieved, but the IC size and design complexity increase
Solution Approach 1:
The patent extracts the pulse generation function from complex clock management circuits (dividers and chopping circuits) and implements it directly within the scan chain flip-flops. The launch and capture pulses are generated by controlling the clock input of the scan chain, eliminating the need for separate divider and chopping circuit blocks, thus reducing IC size and design complexity while maintaining testing accuracy
Solution Approach 2:
The scan chain flip-flops are given multiple functions: they serve both as data storage elements for testing and as pulse generation elements. By controlling the clock input of the scan chain, the same flip-flops generate both launch and capture pulses, eliminating the need for dedicated pulse generation circuits and reducing overall system complexity
2Adaptability or versatility
If additional test registers are added to control dividers for multi-domain testing, then multi-domain at-speed testing capability is improved, but the IC size increases
Solution Approach 1:
The scan chain flip-flops perform dual functions: data storage during testing and pulse generation for multi-domain testing control. By using the existing scan chain infrastructure for both purposes, the patent eliminates the need for additional test registers, thereby maintaining multi-domain testing capability without increasing IC size
Solution Approach 2:
The patent merges the pulse generation control function with the existing scan chain structure. The clock control signals for generating launch and capture pulses are integrated into the scan chain operation, combining multiple functions into a single unified structure rather than adding separate control registers
3Measurement precision
If chopping circuits are included in the functional clock path for pulse extraction, then launch and capture pulses can be generated, but timing overhead increases
Solution Approach 1:
The patent removes the chopping circuit from the functional clock path and instead generates pulses by directly controlling the scan chain clock input. This extraction eliminates the timing overhead introduced by chopping circuits while maintaining the ability to generate accurate launch and capture pulses for at-speed testing
Solution Approach 2:
Instead of extracting pulses from an existing clock signal through chopping circuits (forward approach), the patent inverts the approach by using the scan chain clock control to directly generate the required pulses. This reverse approach eliminates the intermediate chopping stage and its associated timing overhead
Data Source
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AI summary
An integrated circuit (IC), including a clocking system, a plurality of clock gate controllers, and a plurality of clock gates, is provided. During a capture phase of an at-speed testing of the IC, the clocking system generates an at-speed clock signal including launch and capture pulses that are extracted from a reference clock signal based on a capture phase frequency. The plurality of clock gate controllers generates a plurality of enable signals such that for the launch pulse, one enable signal is asserted, and for the capture pulse, the same or different enable signal is asserted. Each of the plurality of clock gates is activated based on an assertion of a corresponding enable signal. Further, during the capture phase, one or more activated clock gates enable the at-speed testing of the IC based on the at-speed clock signal.