Bistable PUF Circuit Using Subthreshold Leakage for Low-Area Stability
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Solution Overview
Problem
Traditional bistable PUF circuit designs face challenges in achieving a balance between low error rates and small area expenditures, often resulting in either large area with low error rates or high error rates with poor stability.
Innovation Solution
A bistable physical unclonable function circuit based on subthreshold leakage current deviation, comprising a time sequence control circuit, decoder, 16 bias voltage converters, and a PUF array, which utilizes a cross-coupled bistable structure and subthreshold region operation to generate response signals with low error rates and small area expenditure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional bistable PUF circuit designs use six or more transistors as switch tubes and deviation entropy source tubes, then the error rate is reduced, but the area expenditure increases
Solution Approach 1:
The patent combines the switch tube and deviation entropy source tube functions into a single transistor structure. The cross-coupled circuit uses transistors that simultaneously serve as both switching elements and sources of process variation, eliminating the need for separate dedicated transistors for each function. This merging reduces the total transistor count from six or more to just four transistors per PUF unit, achieving both low area expenditure and acceptable error rates.
Solution Approach 2:
Each transistor in the cross-coupled structure performs multiple functions: it acts as a switch tube for signal control, a deviation entropy source for generating unique PUF responses, and part of the bistable latching mechanism. This multi-functionality allows the circuit to achieve reliable PUF operation with minimal transistor count, resolving the contradiction between reliability and area efficiency.
2Reliability
If capacitor-preferred preselection mechanism is added to decrease error rate to 10^-9, then the error rate is improved, but the layout area increases to 3001F2
Solution Approach 1:
The patent extracts and removes the capacitor-based preselection mechanism from the PUF circuit structure. By eliminating these large capacitive elements, the design achieves significant area reduction while maintaining acceptable error rates through the inherent process variations captured by the cross-coupled transistor structure, without requiring the 3001F2 layout area.
Solution Approach 2:
The patent replaces expensive, large-area capacitor structures with simple, minimal transistor-based cross-coupled logic that relies on inherent process variations. This substitution uses smaller, more area-efficient components that achieve the same PUF functionality without the need for large capacitive preselection mechanisms.
3Reliability
If cross-coupled comparator-based PUF circuit uses CTAT and SMV to decrease error rate, then the error rate is improved, but the unit layout area increases to 1036F2
Solution Approach 1:
The patent replaces the complex comparator-based mechanical/electrical system with a simpler cross-coupled logic structure. Instead of using comparators with CTAT and SMV compensation circuits, the design uses the natural bistable behavior and process variations of the cross-coupled transistors to generate PUF responses, achieving area efficiency while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit achieves a low error rate of 1.16% and a small layout area of 0.177 μm² per PUF unit, effectively balancing error rate and area expenditure while maintaining robustness and stability.
Implementation Method 1
bistable physical unclonable function circuit based on subthreshold leakage current deviation
Data Source
AI summary
A bistable physical unclonable function circuit based on subthreshold leakage current deviation comprises a time sequence control circuit, a decoder, 16 bias voltage converters and a PUF array, wherein the time sequence control circuit is used for generating a precharge signal and an enable signal, the decoder is used for converting an external stimulus signal into 16 decoded signals under the control of the precharge signal and the enable signal, the kth bias voltage converter is used for converting the kth decoded signal into a kth word line signal which is input to the PUF array, the PUF array is used for generating 16 response signals under the control of the precharge signal and the 16 word line signals, and comprises four PMOS transistors, four NMOS transistors, two two-input NAND gates and sixteen PUF units, and each PUF unit comprises two NMOS transistors.