Reversible Logic IC Self-Test for BTI Fault Coverage
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Solution Overview
Problem
Current IC testing methods, such as Dual Mode Redundancy (DMR) and Triple Mode Redundancy (TMR), are inadequate in detecting Bias Temperature Instability (BTI)-related failures, which can lead to undetected operation failures in critical applications, especially where human safety is at risk, due to the identical nature of modules affecting all similarly and not providing complete fail-safe operation.
Innovation Solution
Implementing conservative reversible logic using extended flip-flops and Fredkin gates within the IC, allowing for 100% transition fault coverage and stuck-at fault coverage through self-testing with just two test vectors, ensuring comprehensive detection of BTI-related setup and hold violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DMR or TMR is used to ensure fail-safe IC operation, then reliability is improved, but measurement precision deteriorates because identical modules cannot detect BTI-related violations
Solution Approach 1:
The patent applies asymmetry by using non-identical modules in the redundancy system. Specifically, it employs conservative reversible logic gates (such as Fredkin gates) that have different operational characteristics from traditional CMOS logic gates. This asymmetry allows the test modules to experience different BTI stress conditions than the application modules, enabling detection of BTI-related violations that would be missed by identical DMR/TMR modules.
Solution Approach 2:
The patent introduces conservative reversible logic gates as intermediary test modules between the application modules and the output. These intermediary gates serve a dual purpose: they perform the same logical function as the application modules while simultaneously acting as sensors that detect BTI-induced timing violations by monitoring their own operational integrity.
2Measurement precision
If conservative reversible logic is implemented for self-testing, then measurement precision is improved with 100% fault coverage, but device complexity increases
Solution Approach 1:
The patent applies universality by designing conservative reversible logic gates that perform multiple functions simultaneously. The same gates that execute the application's logical operations also serve as test modules that detect BTI-related faults. This multi-functionality eliminates the need for separate dedicated test circuits, thereby reducing overall device complexity while achieving 100% fault coverage.
Solution Approach 2:
The patent merges the application logic and test logic into a single integrated structure. The conservative reversible logic gates are designed to perform both the computational function required by the application and the self-test function required for fault detection. This merging of functions reduces the number of components needed and simplifies the overall circuit architecture.
3Reliability
If extended flip-flops and Fredkin gates are used for self-testing, then reliability is improved with comprehensive BTI detection, but ease of manufacture deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the operational parameters of standard CMOS technology to implement conservative reversible logic gates. By adjusting design parameters such as transistor sizing, gate geometry, and bias conditions, the patent enables the fabrication of Fredkin gates and extended flip-flops using conventional CMOS manufacturing processes, thereby maintaining ease of manufacture while achieving improved reliability.
Data Source
AI summary
During a test for integrated circuit aging effects, contents of a first set of flip flop circuits are transferred to a second set of flip flop circuits. A first test value is applied to inputs of a combinatorial logic circuit and outputs from the combinatorial logic circuitry are provided to inputs of the first set of flip flop circuits. The combinatorial logic circuitry is reversible and conservative. The outputs from the first flip flop circuits are compared to the first test value to determine if there is a match. A second test value is applied to the inputs of the combinatorial logic circuitry and the outputs from the combinatorial logic circuitry are provided to inputs of the first set of flip flop circuits. The outputs from the first flip flop circuits are compared to the second test value to determine if there is a match, and when the test mode finishes, contents of the second set of flip flop circuits are transferred to the first set of flip flop circuits.