Multi-Mode Frequency Divider for 50% Duty Cycle Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-mode frequency dividers, both synchronous prescaler-counter based and asynchronous cascade structures, are unable to generate an output clock signal with a duty cycle of 50% at any division ratio.
Innovation Solution
A multi-mode frequency division circuit that includes a frequency division factor processor, frequency divider, and logic operator, which decomposes the frequency division factor into sub-factors and selectively outputs them based on a clock signal to generate a frequency division clock signal, and then samples it using rising and falling edges to produce an output clock signal with a 50% duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a synchronous prescaler-counter based structure or asynchronous cascade structure is used for frequency division, then the frequency division function is achieved, but the output clock signal cannot have a duty cycle of 50% at any division ratio
Solution Approach 1:
The frequency division factor N is segmented into two sub-factors M1 and M2, where M1 ≤ N/2 and M2 = N - M1. The circuit selectively applies different sub-factor combinations based on the desired division ratio, enabling 50% duty cycle output by choosing appropriate segments of the division factor
Solution Approach 2:
The circuit dynamically selects between different frequency division paths (first sub-factor M1 or second sub-factor M2) based on control signals. This dynamic selection allows the circuit to adapt to different division ratios while maintaining 50% duty cycle, transforming a static circuit into a dynamically configurable frequency divider
2Productivity
If asynchronous cascade structure is used, then frequency division is achieved, but jitter accumulates
Solution Approach 1:
The circuit uses feedback mechanisms where the output of the frequency divider is fed back to control the selection of sub-factors. This feedback ensures that the division process maintains proper timing relationships and prevents jitter accumulation by continuously adjusting the division path based on actual output conditions
3Reliability
If prescaler based on divide-by-2/3 is used, then jitter accumulation is avoided, but 50% duty cycle output at any division ratio is not achieved
Solution Approach 1:
The circuit changes the division parameter dynamically by selecting different sub-factors (M1 or M2) based on the desired output. Instead of using a fixed divide-by-2/3 prescaler, the circuit adjusts the division factor in real-time to achieve both jitter control and 50% duty cycle across various division ratios
Data Source
AI summary
The disclosure provides a multi-mode frequency division circuit including a frequency division factor processor, a frequency divider, and a logic operator. The frequency division factor processor receives the frequency division factor, decomposes the frequency division factor to obtain a first sub-frequency division factor and a second sub-frequency division factor, and outputs the first sub-frequency division factor or the second sub-frequency division factor according to a frequency division clock signal. The divider performs frequency division on the clock signal based on the first sub-frequency division factor or the second sub-frequency division factor to generate the frequency division clock signal. The logic operator sequentially samples the frequency division clock signal according to the rising edge and falling edge of the clock signal to generate a first signal and a second signal, and the logic operator generates an output clock signal according to the first signal, the second signal, and an indication signal.