Pixel Counter Circuit for Low-Power Sampling Pulse Generation
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Solution Overview
Problem
Existing binary counter systems require a large number of combinational logic circuits to generate multiple square wave pulse sampling signals, leading to increased power consumption and layout area occupation.
Innovation Solution
A counter design incorporating a start-up circuit and alternately cascaded first and second combinational logic circuits, which output the clock signal and its inverted signal respectively, along with low-level signals in specific time periods, to divide the clock signal and generate multiple sampling pulse signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of combinational logic circuits are used to generate multiple square wave pulse sampling signals, then the counting function is achieved, but the power consumption increases
Solution Approach 1:
The patent merges the functions of multiple combinational logic circuits into a single counter circuit that generates multiple square wave pulse sampling signals simultaneously. The counter circuit integrates the counting function and the generation of multiple sampling signals (first, second, and third sampling signals) into one unified structure, thereby reducing the total number of logic circuits and lowering power consumption while maintaining reliable counting functionality.
2Reliability
If a large number of combinational logic circuits are used to generate multiple square wave pulse sampling signals, then the counting function is achieved, but the layout area occupation increases
Solution Approach 1:
The patent merges the functions of multiple combinational logic circuits into a single counter circuit that generates multiple square wave pulse sampling signals simultaneously. The counter circuit integrates the counting function and the generation of multiple sampling signals (first, second, and third sampling signals) into one unified structure, thereby reducing the total number of logic circuits and lowering power consumption while maintaining reliable counting functionality.
3Reliability
If multiple combinational logic circuits are used to generate square wave pulse sampling signals, then the sampling signals are generated, but the circuit complexity increases
Solution Approach 1:
The patent merges the functions of multiple combinational logic circuits into a single counter circuit that generates multiple square wave pulse sampling signals simultaneously. The counter circuit integrates the counting function and the generation of multiple sampling signals (first, second, and third sampling signals) into one unified structure, thereby reducing the total number of logic circuits and lowering power consumption while maintaining reliable counting functionality.
Data Source
AI summary
Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.