Configurable NVM Memory Array for Stable Boot-Time Read Reference
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Solution Overview
Problem
During the boot operation of non-volatile memory (NVM), the lack of a stable reference current from a bandgap or current reference block makes NVM read operations unreliable, as reliable trimming and configuration bits are not available, necessitating alternative methods for generating a stable reference current.
Innovation Solution
A reference current is generated using a reference memory cell array, which is formed in the same process as the primary memory cells, allowing for accurate single-ended read operations by averaging currents from multiple memory cells, and enabling differential read operations through test memory cells and their complements, providing flexibility in memory array configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bandgap or current reference block is used to provide reference current, then single-ended read operations can be performed, but the reference current is unstable during boot operation when trimming and configuration bits are not available
Solution Approach 1:
The patent introduces test memory cells as an intermediary mechanism to generate reference current during boot operation. These test memory cells are specifically designated to store trimming and configuration bits, serving as a mediator between the memory array and the reference current generation process, enabling stable reads without relying on bandgap circuits that require unavailable trimming data during startup
Solution Approach 2:
The patent implements preliminary action by pre-configuring test memory cells with trimming and configuration bits before normal operation. This allows the system to have reference current generation capability ready in advance, eliminating the dependency on bandgap circuits during boot operation when such circuits cannot yet provide stable reference current due to unavailable trimming data
2Reliability
If differential read is used with test memory cells, then reliable trimming and configuration bits can be read during boot operation, but the memory array requires additional configuration complexity to support both differential and single-ended read modes
Solution Approach 1:
The patent applies universality by designing memory cells that can function in multiple modes. The same memory cell infrastructure supports both differential read (for boot operation with test memory cells) and single-ended read (for normal operation with user memory cells). The column multiplexor and sense amplifier are configured to handle both read modes, eliminating the need for separate dedicated circuits for each mode and reducing overall system complexity
3Measurement precision
If multiple memory cells are used to generate reference current through averaging, then read accuracy is improved, but the time required to complete the read operation increases
Solution Approach 1:
The patent implements partial action by using a selective subset of memory cells for reference current generation rather than all available cells. The system can dynamically choose the number of test memory cells to average based on the required precision level, allowing optimization between read accuracy and read speed. This partial utilization approach provides sufficient reference current stability without the time penalty of processing excessive cells
Data Source
AI summary
The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.