Nested Clock Gater Simulation Fixes for False X Detection
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Solution Overview
Problem
Existing methods for correcting logic simulation results fail to effectively identify and fix false Xs created by nested clock gaters, leading to inaccuracies in logic simulation due to the combination of real Xs at enable signals of clock gaters, which results in power consumption inefficiencies and simulation pessimism.
Innovation Solution
The proposed system and method analyze combinational circuits at the fan-in cones of enable signals in a chain of nested clock gaters, replace clock gaters with AND gates, and generate fixes to correct false Xs by monitoring clock pins, traversing clock paths, and creating combinatorial circuits to identify and address false Xs at clock gater outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If nested clock gaters are simulated using existing logic simulation methods, then simulation coverage is achieved, but false Xs are generated leading to simulation inaccuracy
Solution Approach 1:
The patent segments the clock gater chain into individual clock gaters and analyzes each one's enable signal separately. By dividing the nested clock gater structure into discrete segments, the method can identify false Xs at each stage rather than treating the entire chain as a single unit, thereby improving simulation accuracy while maintaining result reliability
Solution Approach 2:
The patent introduces an intermediary analysis layer that examines the enable signals of clock gaters before they propagate to sequential elements. This intermediary step acts as a mediator between the clock gater chain and the sequential elements, identifying and correcting false Xs before they contaminate the final simulation results, thus resolving the contradiction between accuracy and reliability
2Measurement precision
If clock gaters are analyzed to identify false Xs, then simulation accuracy improves, but computational complexity increases
Solution Approach 1:
The patent applies local quality by focusing the analysis only on the enable signals of clock gaters and their direct impact on sequential elements, rather than analyzing the entire circuit. This localized approach improves simulation accuracy where it matters most while avoiding unnecessary computational complexity in other parts of the design
Solution Approach 2:
The patent performs partial analysis by examining only the necessary portions of the clock gater chain that can produce false Xs at sequential element inputs. Rather than exhaustively analyzing every possible path, it applies partial action to the critical regions, achieving improved accuracy without the full computational burden of complete circuit analysis
Data Source
AI summary
A computer executable tool fixes gate-level logic simulation when unknowns (Xs) exist in nested clock gater chains to improve simulation accuracy. Due to X-pessimism in logic simulation, false Xs are generated when simulating nested clock gaters, producing incorrect simulation results. The tool analyzes the fan-in cones along a nested clock gater chain to find such false Xs. Furthermore, it generates auxiliary code to be used with logic simulation to eliminate such false Xs. Gate-level simulation can then be repaired to produce correct results for nested clock gaters.