Clock-Aligned Data Serialization Circuit for Higher Bandwidth
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Solution Overview
Problem
Conventional serialization circuits face increased complexity and reduced bandwidth due to multiple clock signals with different phases, leading to mismatched data paths and lower operation speeds, making them unsuitable for high-speed data serialization.
Innovation Solution
A semiconductor device with a clock data operation circuit generating delay clock signals and synchronous data signals in response to parallel data and multi-phase clock signals, using a multiplexer to output serial data with aligned clock and data signals, and a reduced number of transistors in series, which includes a pull-down circuit with NMOS transistors for efficient data serialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional serialization circuits use multiple clock signals with different phases, then data rate can be increased, but system complexity increases and bandwidth decreases
Solution Approach 1:
The patent divides the serialization function into multiple operation circuits (first operation circuit, second operation circuit, etc.), where each circuit handles a specific portion of the parallel data. This segmentation allows each circuit to operate with simpler, fewer clock phases while collectively achieving high data rates, thereby reducing overall system complexity.
Solution Approach 2:
The patent transitions from using multiple clock phases in the time domain to using multiple parallel operation circuits in the spatial dimension. Instead of increasing clock frequency and phases, the invention adds parallel processing paths that can be clocked at lower frequencies, thus achieving high data rates without proportionally increasing system complexity.
2Productivity
If conventional serialization circuits use multiple clock signals with different phases, then data rate can be increased, but bandwidth decreases
Solution Approach 1:
By segmenting the serialization function into multiple operation circuits, each circuit can be optimized with fewer transistors in series. This reduces the total parasitic capacitance in each signal path, thereby maintaining or increasing bandwidth while achieving high data rates through the combined output of multiple circuits.
Solution Approach 2:
The patent changes the architectural parameter from a single complex clock distribution system to multiple simpler operation circuits. This parameter change reduces the number of transistors in the critical signal path, lowering parasitic capacitance and increasing bandwidth, while the parallel structure of multiple circuits maintains the high data rate.
3Productivity
If conventional serialization circuits increase the number of transistors in series, then more clock phases can be handled, but operation speed decreases
Solution Approach 1:
The patent segments the serialization function into multiple independent operation circuits, where each circuit handles a subset of the parallel data. Each operation circuit uses a reduced number of transistors in series compared to a single comprehensive circuit, thereby reducing parasitic capacitance and increasing operation speed, while the parallel combination achieves the required data rate.
Solution Approach 2:
The patent combines the outputs of multiple operation circuits (each with fewer transistors in series) to achieve the overall serialization function. This merging approach allows the system to handle more data parallelly without increasing the transistor count in each individual signal path, thus maintaining high operation speed while achieving high data rates.
Data Source
AI summary
A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.