Clock Delay Circuit Topology for Duty Cycle Preservation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Delay circuits used in clock signal distribution can cause supply/ground disturbances and duty cycle distortion, affecting the performance of circuits that operate on clock edges, particularly in systems with varying delays for rising and falling edges across PVT variations.
Innovation Solution
A delay circuit design that includes a multiplexer selecting between two delay paths, each with a delay device and inverters, to maintain the input clock signal's duty cycle by ensuring equivalent delays for rising and falling edges, reducing duty cycle distortion and minimizing supply/ground disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a delay circuit is used to delay clock signals, then the clock signal timing is adjusted, but duty cycle distortion occurs and supply/ground disturbances are generated
Solution Approach 1:
The delay circuit is segmented into multiple delay paths (first delay path with first delay device, second delay path with second delay device). Each path handles different signal edges separately, allowing independent optimization of delay characteristics for rising and falling edges, thereby reducing duty cycle distortion while maintaining the required clock signal delay
Solution Approach 2:
Different delay devices are used in different paths to optimize for specific signal characteristics. The first delay path may use devices optimized for rising edges while the second delay path uses devices optimized for falling edges, ensuring each path has the appropriate local quality for its function, which reduces overall duty cycle distortion
2Loss of time
If a delay circuit is used to delay clock signals, then the clock signal timing is adjusted, but supply/ground disturbances are generated
Solution Approach 1:
The multiplexer acts as an intermediary that selectively couples either the first delay path or second delay path to the output based on the input signal edge. This intermediary mechanism allows the circuit to switch between different delay paths, reducing simultaneous switching activity and thereby minimizing supply/ground disturbances while still achieving the required clock signal delay
3Adaptability or versatility
If delay devices are used with different delays for rising and falling edges, then timing flexibility is improved, but duty cycle distortion increases
Solution Approach 1:
The circuit dynamically selects which delay path to use based on the input signal edge type (rising or falling). The multiplexer changes its coupling configuration dynamically, selecting the first delay path for one edge type and the second delay path for the other edge type. This dynamic adaptation allows the circuit to maintain timing flexibility while compensating for differential delays to reduce duty cycle distortion
Data Source
AI summary
In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.