I3C Bus Start-Stop Detection for Reliable Slave Signal Latching
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Solution Overview
Problem
The I3C bus lacks a safe setup time and hold time for the slave device to latch the start signal, leading to malfunctions due to the absence of a core circuit setup time and hold time, and the generation of repeat start and stop patterns complicates signal detection.
Innovation Solution
A start-and-stop detecting apparatus connected to the I3C bus, comprising first and second detecting circuits and OR gates, which generate control signals and output signals to accurately identify start and stop patterns, ensuring proper data reception and transmission by enabling and resetting detectors to generate start and stop signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data signal level state changes at the first negative edge of the clock signal according to I3C bus specifications, then the I3C bus can achieve faster data transmission, but the slave device has no safe setup time and hold time to latch the start signal, causing malfunction
Solution Approach 1:
The patent applies preliminary action by detecting the start pattern before the actual data transmission begins. The detecting circuit identifies the start pattern at the first negative edge of the clock signal and generates the start signal in advance, providing the slave device with sufficient setup time and hold time to latch the signal reliably, thus resolving the contradiction between fast transmission and reliable operation
Solution Approach 2:
The patent introduces a detecting circuit as an intermediary between the I3C bus signal lines and the slave device. This intermediary circuit separates the fast edge-triggered start pattern detection from the slave device's data latching operation, allowing the slave device to operate at its own reliable timing while still benefiting from the fast I3C bus protocol
2Adaptability or versatility
If multiple start patterns and stop patterns are generated in the time interval between start and stop patterns, then repeat start and stop patterns can be detected, but the signal detection complexity increases
Solution Approach 1:
The patent extracts the start pattern and stop pattern detection functions into separate dedicated detecting circuits. The start detecting circuit specifically monitors for start patterns while the stop detecting circuit monitors for stop patterns, allowing each circuit to be optimized for its specific function and reducing overall detection complexity despite the need to handle multiple repeat patterns
Solution Approach 2:
The patent segments the detecting apparatus into distinct functional modules: a start detecting circuit with first and second start detecting units, a stop detecting circuit with first and second stop detecting units, and OR gates for signal combination. This segmentation allows each module to handle specific aspects of pattern detection independently, managing complexity through modular design
Data Source
AI summary
A start-and-stop detecting apparatus for an I3C bus is provided. The start-and-stop detecting apparatus is connected with a serial data line and a serial clock line. The start-and-stop detecting apparatus includes a first start detecting circuit, a second start detecting circuit and a first OR gate. The first start detecting circuit receives a data signal, a clock signal and a reset signal, and generates a first control signal and a first output signal. The second start detecting circuit receives the data signal, the clock signal, the reset signal and the first control signal, and generates a second output signal. A first input terminal of the first OR gate receives the first output signal. A second input terminal of the first OR gate receives the second output signal. An output terminal of the first OR gate generates a start signal.