Boosted Bit Line Driver for NAND SSL Switching Margin
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Solution Overview
Problem
In low voltage integrated circuits, such as those used in NAND flash memory, the select string line (SSL) on/off margin for self-boosting operations is narrow due to smaller device areas and lower operation voltages, making it challenging to maintain effective switching and prevent charge leakage or program disturbance in NAND strings.
Innovation Solution
A device comprising a first power supply circuit connected to a low voltage external power supply and a second power supply circuit connected to an on-chip charge pump, with a control circuit and voltage driver to generate and boost control signals, allowing a select gate transistor to be turned on or off based on voltage differences, thereby enhancing the switching margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If lower operation voltages are used in advanced CMOS technology, then power consumption is reduced and device area is smaller, but the SSL on/off operating margin becomes narrower
Solution Approach 1:
The patent divides the power supply system into two separate circuits: a first power supply circuit providing a lower voltage (e.g., 1.8V) for normal operation, and a second power supply circuit providing a higher voltage (e.g., 3.3V) specifically for SSL gate control. This segmentation allows each circuit to be optimized independently, enabling strong SSL switching margins while maintaining low overall power consumption.
Solution Approach 2:
The patent introduces a voltage driver as an intermediary component between the control logic and the SSL gate. This voltage driver receives control signals from the low-voltage domain and outputs appropriately scaled voltages to the SSL gate, mediating between the low operating voltages and the higher voltage required for reliable SSL switching.
2Area of stationary object
If smaller device area is used, then integration density increases, but the window of strong off condition for self-boosting operation becomes smaller
Solution Approach 1:
By segmenting the power supply into separate low-voltage and high-voltage circuits, the patent enables small device area through advanced CMOS scaling while maintaining reliable SSL off conditions through the higher voltage provided by the second power supply circuit during self-boosting operations.
Solution Approach 2:
The patent dynamically changes the voltage parameter supplied to the SSL gate based on operational requirements. During self-boosting operations, the higher voltage from the second power supply circuit is applied to ensure strong off conditions, while during normal operation, the lower voltage is used to minimize power consumption and device area.
Data Source
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AI summary
Memory device configured to increase the select string line (SSL) on/off margin for NAND array self-boosting operation. The memory device comprises NAND strings (362) and corresponding bit lines BL (322) connected to String Select Lines SSL (312), a first power supply circuit (318) to distribute a first power supply voltage (VDD1), a second power supply circuit (314) to distribute a second power supply voltage (VDD2) higher than the first power supply voltage (VDD1), and a page buffer (319) that generates program/inhibit outputs (DL, DLB) having a level between the first power supply voltage (VDD1) and a first reference voltage (VSS). Data line drivers drive nodes (374) coupled to corresponding bit lines BL (322) with a first voltage or a second voltage between the second power supply voltage (VDD2) and a second reference voltage (VSS). A data line driver includes a first switch transistor (325) connected between the data line node (374) and the second power supply circuit (314) providing the second power supply voltage (VDD2), a second switch transistor (364) connected between the data line node (374) and the second voltage reference (375) providing the second reference voltage (VSS), and a boost circuit (317, 363) configured to boost the gate of the first switch transistor (325) above the first supply voltage level (VDD1) to turn on the first switch transistor (325).