Memory Array Layout for Accurate Boot-Time Differential Read
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Solution Overview
Problem
During the boot operation of non-volatile memory (NVM), the lack of a stable reference current from a bandgap or current reference block leads to unreliable read operations, as reliable trimming and configuration bits are not available, necessitating a differential read method that does not depend on a stable reference current.
Innovation Solution
A primary memory array is configured with test memory cells and user memory cells, where test memory cells store trimming and configuration bits for differential read, and a reference current is generated using a reference memory cell array that mimics the primary memory cell array's process and temperature responses, allowing for adjustable and accurate single-ended read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a bandgap or current reference block is used to provide reference current for single-ended read operations, then read accuracy is improved, but during boot operation the reference current is unstable and unreliable
Solution Approach 1:
The patent performs differential read operations during boot operation before the bandgap reference current is stable. Test memory cells are read using differential read methodology which does not require stable reference current, allowing the system to bootstrap itself and generate stable reference current for subsequent single-ended read operations.
Solution Approach 2:
The patent changes the read operation parameter from single-ended to differential during boot operation. Differential read operations use a different sensing mechanism that compares currents from direct and complementary cells, eliminating dependency on stable reference current while maintaining read accuracy for trimming and configuration bits.
2Reliability
If differential read is used during boot operation, then reliability of read is improved without stable reference current, but device complexity increases due to additional circuitry
Solution Approach 1:
The patent designs the memory array with dual-read capability, where the same memory cells can be read using either differential read methodology during boot operation or single-ended read methodology during normal operation. This multi-functionality allows the system to handle both boot and normal operations with a unified memory structure.
Solution Approach 2:
The memory array performs self-configuration during boot operation by reading test memory cells using differential read. The trimming and configuration bits are automatically applied to optimize the bandgap reference current and other parameters, enabling the system to self-calibrate without external intervention.
3Reliability
If test memory cells are stored in the primary memory array, then trimming and configuration bits are available for boot operation, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory array into distinct functional regions: test memory cells for storing trimming and configuration bits, and user memory cells for storing data. This segmentation allows test cells to be optimized for boot operation requirements while user cells maintain standard specifications, reducing overall manufacturing precision requirements.
Solution Approach 2:
The patent creates complementary test memory cells that are logical inverses of the direct test cells. This copying approach with inversion allows differential read to effectively cancel out process variations and manufacturing tolerances, as the complementary cells experience opposite variations that compensate for each other during comparison.
Data Source
AI summary
The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.