Analog Neural Network Circuit for Low-Power Product-Sum Computing
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Solution Overview
Problem
Current neural network circuits face challenges in integrating large-scale neural networks on a chip due to increased power consumption and operation delay times, especially with repetitive memory access, and are limited in complexity and accuracy for AI tasks like image recognition and language translation.
Innovation Solution
A neural network circuit design incorporating D/A converters, analog-to-digital multipliers with MOS transistors, and an analog activation function circuit, which performs product-sum operations and activation functions efficiently, reducing power consumption and memory access frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital circuit operation is used for neural network circuits, then high recognition accuracy can be achieved, but power consumption and operation delay time increase significantly
Solution Approach 1:
The patent replaces conventional digital circuit operations with analog circuit operations for neural network computations. Specifically, analog multipliers use current mirrors to perform multiplication operations, and analog adders use current summation, eliminating the need for digital-to-analog conversion and repeated memory access. This substitution of digital (mechanical-like discrete) operations with analog (continuous) operations reduces power consumption while maintaining computational accuracy for AI inference tasks.
2Productivity
If large-scale neural network circuits are integrated, then AI processing capability improves, but area occupied by capacitive elements or switches increases
Solution Approach 1:
The patent merges multiple functional elements into unified analog circuit blocks. The analog multiplier integrates switching elements and capacitive elements into a single current mirror-based multiplication unit, eliminating the need for separate memory units and conversion circuits. This consolidation reduces the total chip area required for large-scale neural network integration while maintaining full AI processing capability through direct analog computation of weighted sums and activation functions.
Solution Approach 2:
The patent extracts and eliminates unnecessary digital processing stages from the neural network circuit. By removing digital-to-analog converters, analog-to-digital converters, and associated memory units, the design reduces chip area occupation. The analog computation approach directly calculates neuron outputs without requiring intermediate digital storage and conversion, freeing up significant chip real estate for larger network integration.
3Measurement precision
If repetitive memory access is performed for neural network operations, then computation accuracy is maintained, but operation delay time increases
Solution Approach 1:
The patent implements continuous analog computation that eliminates discrete memory access cycles. The analog multipliers and adders continuously process input signals through current mirrors and summation nodes, maintaining computation accuracy through physical law-based calculations rather than discrete digital steps. This continuous action removes the time delays associated with repeated memory reads and writes, enabling real-time neural network inference.
4Use of energy by moving object
If analog circuit operations are used for neural networks, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent designs universal analog circuit blocks that perform multiple neural network operations. The current mirror-based multiplier can handle both weight application and activation function computation, while the analog adder serves as both a summation unit and a signal distribution node. This multi-functionality reduces the number of separate circuit elements needed, managing device complexity while achieving low power consumption through unified analog processing architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of large-scale neural networks with high-speed and low-power analog operations on a chip, improving AI processing efficiency and recognition accuracy while reducing power consumption and operation delays.
Implementation Method 1
Each of the analog-to-digital multipliers includes an output node to which the analog-to-digital input voltage is connected, and a MOS transistor provided corresponding to at least one bit signal corresponding to the digital signal. The MOS transistor has a source terminal, a drain terminal, and a gate terminal. The source terminal and the drain terminal are connected to the output node. A voltage based on the bit signal is applied to the gate terminal. A charge signal corresponding to the product of the analog input voltage and the bit signal is output as the multiplication result.
Data Source
AI summary
A neural network circuit having a plurality of analog-to-digital multipliers generates an analog product-sum voltage corresponding to the sum of charge signals of each of the analog-to-digital multipliers.