Latch-Based FIFO ATPG Testing for Area-Efficient Path Coverage
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Solution Overview
Problem
FIFO buffers constructed from latches in integrated circuit devices face limitations in testing capabilities, particularly in testing the write and read paths individually and for stuck-at-1 faults, which restricts comprehensive testing and area reduction efforts.
Innovation Solution
A system with a write data register, read data register, and FIFO buffer comprising banks of latches, enabled by internal write and read enable signals, allows for advanced testing modes like ATPG and LBIST, enabling individual path testing and fault detection through specific signal control and phase management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If latches are used to replace flip flops in FIFO buffers, then area is reduced by 45% to 50%, but testing capability is limited and cannot perform individual path testing or stuck-at-1 fault detection
Solution Approach 1:
The patent segments the enable signal control by introducing separate internal write enable and internal read enable signals that can be independently controlled during test mode. This segmentation allows individual testing of write path and read path, and enables stuck-at-1 fault detection on latch enable pins, while maintaining the area-efficient latch-based FIFO structure.
2Ease of operation
If latches are made transparent during testing, then data path testing is enabled, but individual path testing and stuck-at-1 fault detection remain impossible
Solution Approach 1:
The patent introduces dynamic control of latch transparency through mode-dependent enable signal generation. In test mode, the internal write enable and internal read enable signals can be independently asserted to make specific latch banks transparent, enabling flexible individual path testing. In functional mode, the latches operate with normal enable signals for data storage and retrieval.
3Productivity
If conventional testing methods are used on latch-based FIFOs, then simple data path testing is possible, but comprehensive testing including individual paths and stuck-at-1 faults cannot be achieved
Solution Approach 1:
The patent implements multi-functional control circuitry that handles both functional mode and test mode operations. The same internal write enable and internal read enable signals serve dual purposes: controlling latch operation during normal FIFO functionality and enabling various test configurations (individual path testing, stuck-at-1 fault detection) during test mode, thereby achieving comprehensive testing without proportionally increasing hardware complexity.
Data Source
AI summary
Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.