Multi-Phase Clock Circuit Topology for Stable 8-Phase Generation
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Solution Overview
Problem
Existing multi-phase clock signal generators face challenges in generating a large number of clock signals with increasing phase delays, such as 8-phase signals, due to limitations in phase accuracy, robustness, and frequency range, particularly when using phase interpolator circuits and logic gates which can lead to phase swapping and reduced maximum frequency of operation.
Innovation Solution
A circuitry and method that uses a loop configuration of logic components, where each component receives three input signals and masks out the third input signal based on the first and second input signals, ensuring a fixed order of phase delays and doubling the number of output clock signals, thereby enhancing phase accuracy and supporting high frequencies without the need for D-type flip-flop circuits or latches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If phase interpolator circuits are used to generate 8-phase clock signals, then the number of clock signals can be increased, but phase accuracy deteriorates and requires calibration to track temperature variations
Solution Approach 1:
The circuit divides the generation of 8-phase clock signals into two separate 4-phase clock signal generation paths. Each path uses identical logic gate structures operating in parallel, with outputs combined through masking operations. This segmentation eliminates the need for complex phase interpolators while maintaining high phase accuracy through symmetric design.
Solution Approach 2:
The invention changes the operational parameters by using logic gates configured to operate at different phases (0°, 90°, 180°, 270°) rather than using a single phase interpolator circuit. This parameter-based approach allows each logic gate to operate within its optimal frequency range while maintaining consistent phase relationships across all 8 output phases.
2Productivity
If logic gates and latches are used in multi-phase clock generation, then clock signals can be generated, but robustness deteriorates and maximum frequency of operation is reduced
Solution Approach 1:
The invention extracts and removes latches from the clock generation circuitry, relying solely on combinational logic gates. This elimination of sequential elements (latches) removes the inherent robustness issues and frequency limitations associated with latch-based designs, while still achieving the required multi-phase output through careful logic gate configuration.
Solution Approach 2:
Instead of using latches to store and transfer clock phases sequentially, the invention inverts the approach by using combinational logic gates that simultaneously generate all 8 phases from 4 input phases. This inversion from sequential to parallel operation eliminates the robustness problems of latch-based designs.
3Measurement precision
If phase interpolator circuits with programmable delay lines are used, then phase accuracy can be improved, but input frequency range is limited to a narrow frequency range
Solution Approach 1:
The logic gates in the invention are designed to perform multiple functions: they simultaneously generate phase-shifted clock signals, provide masking operations, and maintain signal integrity across a wide frequency range. This multi-functionality eliminates the need for frequency-specific calibration required by programmable delay lines, enabling operation across a broad input frequency spectrum.
4Quantity of substance
If a large number of clock signals are generated using existing architectures, then the requirements for high-speed converters can be met, but phase swapping occurs and reduces reliability
Solution Approach 1:
The invention introduces asymmetric masking operations in the logic gate configuration where specific logic gates receive inverted versions of input clock signals. This asymmetric treatment of symmetric input signals creates an inherent phase ordering mechanism that prevents phase swapping, as each output phase has a unique combination of input signals that defines its position in the phase sequence.
Data Source
Figure 1a~1b
Figure 2a
Figure 2b~2c
AI summary
A circuitry (100; 200) for generating output clock signals with increasing phase delays (O000, O225, O090, O315, O180, OO045, O270, O135) comprises: an input receiving input clock signals with increasing phase delays (IN_000, IN_090, IN_180, IN_270), wherein the output clock signals are twice as many as the input clock signals; logic components (110a-h; 210a-h) connected in a loop (112; 212) with an output from a component connected as a first input to a following component, wherein the output is further connected as a second input to an oppositely positioned component; wherein each component (110ah; 210a-h) receives the first, the second and a third input signal; wherein pairs of oppositely positioned components receive a common input clock signal and mask out the third input clock signal based on logic state of first and second input signals such that the outputs are phase shifted by 180 degrees; and wherein the circuitry (100; 200) outputs the output clock signals based on outputs from each component.