Duty-Cycle Corrector Circuit for Clock Disable Recovery
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Solution Overview
Problem
Existing duty-cycle correction methods in electronic devices fail to maintain accurate duty-cycle regulation during operation, especially when input clock signals are disabled, leading to error signal saturation and distorted clock signals upon reactivation.
Innovation Solution
Incorporating a clock detector to disable duty-cycle correction when the input clock signal is disabled, using an integrator circuit and amplifier circuit with an electrically controllable switch to prevent error signal saturation and ensure accurate duty-cycle correction upon reactivation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty-cycle correction is continuously applied, then duty-cycle accuracy is improved, but error signal saturation occurs when input clock is disabled
Solution Approach 1:
The clock detector circuit monitors the input clock signal in advance and proactively disables the duty-cycle correction circuit before error signal saturation can occur. This preliminary detection and prevention mechanism ensures that when the input clock is disabled, the correction circuit is already inactive, preventing the integrator from saturating while maintaining accurate duty-cycle correction when the clock is active.
2Duration of action of stationary object
If duty-cycle correction is applied during clock disablement, then continuous regulation is maintained, but distorted clock signals are generated upon reactivation
Solution Approach 1:
The clock detector provides feedback about the input clock signal state to the duty-cycle correction circuit. When the input clock is disabled, the detector signals the correction circuit to disable, preventing integration of invalid signals that would cause distortion. When the clock is reactivated, the feedback immediately enables correction again, ensuring clean signal regeneration without distortion.
3Duration of action of moving object
If amplifier circuit remains enabled during clock disablement, then duty-cycle correction continuity is improved, but error signal levels become inappropriate
Solution Approach 1:
The system performs preliminary disabling of the amplifier circuit through the clock detector before error signal degradation can occur. By detecting clock disablement in advance and immediately disabling the correction circuit, the system prevents the integrator output from reaching saturation levels, preserving error signal integrity for rapid reactivation.
Data Source
AI summary
Apparatuses and methods for correcting a duty-cycle of a clock signal are disclosed. An apparatus includes an integrator circuit, an amplifier circuit, and an electrically controllable switch. The integrator circuit is configured to provide an integrator signal indicating substantially an integral of a corrected clock signal. The amplifier circuit is configured to be disabled responsive to a detection that an input clock signal is disabled. The amplifier circuit includes a first amplifier input terminal and a second amplifier input terminal. The electrically controllable switch is configured to selectively electrically connect the first amplifier input terminal to the second amplifier input terminal responsive to the detection that the input clock signal is disabled. A method of correcting a duty-cycle of an input clock signal includes adjusting a corrected duty-cycle of the corrected clock signal responsive to a first error signal and a second error signal from the amplifier circuit.