Signal Transition Control Circuit for Asymmetric EMI Reduction
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Solution Overview
Problem
Existing control circuits for signal rising and falling times in electronic circuits can only adjust these parameters symmetrically, which may not adequately address electromagnetic interference (EMI) issues, potentially damaging components.
Innovation Solution
A control circuit comprising series-connected data flip-flops, controllable delay circuits, and current source circuits that allow for asymmetric and elastic adjustment of signal rising and falling times by varying the delay amounts of controllable delay circuits, enabling independent control of rising and falling times based on clock signal cycle length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If symmetric adjustment of rising time and falling time is used in control circuits, then the circuit structure is simple, but the EMI reduction effectiveness is insufficient
Solution Approach 1:
The control circuit is segmented into multiple independent controllable delay circuits (first, second, third, fourth delay circuits), each controlling different aspects of the output signal transitions. This segmentation allows independent adjustment of rising time and falling time, enabling asymmetric control to effectively reduce EMI while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The patent implements asymmetric control by allowing different delay amounts for rising edge and falling edge transitions. The controllable delay circuits can be configured with different delay values (e.g., first and third delay circuits for rising edge, second and fourth for falling edge), enabling optimized EMI reduction for each transition type independently, which directly addresses the limitation of symmetric adjustment in prior art
2Object-affected harmful factors
If multiple controllable delay circuits are added to enable asymmetric adjustment, then the EMI reduction effectiveness is improved, but the control circuit complexity increases
Solution Approach 1:
The control circuit is divided into multiple functional modules (controllable delay circuits) that can be independently configured. Each delay circuit handles specific transition control, allowing the system to achieve superior EMI reduction through asymmetric adjustment while maintaining modular architecture that simplifies design and maintenance
Solution Approach 2:
The controllable delay circuits are designed with universal functionality, where each circuit can be configured for different delay requirements. The same circuit architecture serves multiple purposes (controlling different signal transitions), reducing the need for entirely separate dedicated circuits for each function and thereby managing overall complexity
3Adaptability or versatility
If delay amounts of controllable delay circuits are increased to extend adjustment range, then the adaptability is improved, but the signal transition time control precision may be affected
Solution Approach 1:
By segmenting the delay control into multiple smaller delay stages (first, second, third, fourth controllable delay circuits), each circuit can provide fine-grained delay adjustment. This segmentation allows the system to achieve both wide overall adjustment range through cumulative delays and high precision through incremental control at each stage, avoiding the need for large single-step delays that would reduce precision
Data Source
AI summary
A control circuit for controlling signal rising time and falling time is provided. The circuit includes multiple data flip-flops, multiple controllable delay circuits, and multiple current source circuits. The data flip-flops are triggered by clock signals to output a plurality of data signals. The controllable delay circuits delay the data signals, based on corresponding delay amounts, to generate a plurality of activation signals. Each of the current source circuits determines whether to output a unit current to a signal output terminal according to a level of one of the activation signals. Rising or falling time for an output signal of the signal output terminal to rise or fall to a predetermined level is determined according to a cycle time length of the clock signal and the delay amount of each of the controllable delay circuits.