Stacked SRAM Cell Layout for Low-Voltage Write and CIM Density
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Solution Overview
Problem
Existing SRAM devices face challenges in write ability, which affects minimum operating voltage for low power operation, and when applied to CIM applications, they occupy a large area, leading to low computational density and increased process complexity.
Innovation Solution
The use of a stacked transistor structure, such as a CFET, enhances write ability in SRAM devices by configuring an 11-transistor SRAM cell with reconfigurable schemes to perform logic gate functionalities without additional NFET/PFET sizing processes, thereby mitigating the write half-selected disturb issue and reducing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 6T or 8T SRAM cell structures are used, then the device area is reduced, but the write ability is insufficient and minimum operating voltage is high
Solution Approach 1:
The patent transitions from planar transistor arrangements to a stacked three-dimensional transistor structure, where transistors are vertically stacked to increase effective channel width without increasing lateral footprint. This dimensional change enables enhanced write ability while maintaining compact area and reducing minimum operating voltage requirements.
Solution Approach 2:
The patent combines multiple transistor functions into a unified stacked structure where NFET and PFET transistors are vertically integrated. This merging allows shared control mechanisms and reduced peripheral circuitry, improving write ability while lowering the minimum operating voltage compared to traditional separate transistor layouts.
2Reliability
If write assist techniques are introduced to improve write ability, then write ability is enhanced, but SRAM macro area increases and additional power is consumed
Solution Approach 1:
By stacking transistors vertically, the patent achieves enhanced write ability without increasing the lateral macro area. The three-dimensional configuration packs more functional transistors into the same footprint, eliminating the need for additional write assist circuitry that would expand the macro area.
Solution Approach 2:
The stacked transistor structure serves multiple functions simultaneously: it provides the storage function of traditional SRAM cells while also enhancing write ability through increased effective channel width. This multi-functionality eliminates the need for separate write assist techniques, maintaining compact macro area.
3Reliability
If NFET and PFET effective channel widths are optimized separately to improve write ability, then write ability is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The stacked structure merges NFET and PFET fabrication into a unified process flow, where both transistor types are formed simultaneously in the same vertical stack. This combined approach simplifies manufacturing by eliminating separate optimization steps for NFET and PFET channel widths, reducing process complexity while maintaining enhanced write ability.
Solution Approach 2:
The patent changes the structural parameter from separate lateral transistor arrangements to a unified vertical stack, where the effective channel width is determined by the stacked configuration rather than individual transistor sizing. This parameter change simplifies manufacturing by removing the need for separate NFET/PFET width optimization processes.
4Adaptability or versatility
If SRAM cells are used for compute-in-memory applications, then logic gate operations are enabled, but area consumption increases and computational density decreases
Solution Approach 1:
The stacked transistor structure enables six types of logic gate functionalities within a compact vertical footprint, achieving high computational density by utilizing the third dimension. This three-dimensional configuration packs more computational functionality into unit area compared to planar SRAM implementations.
Solution Approach 2:
The unified stacked SRAM cell structure serves dual purposes: it maintains standard SRAM storage functionality while simultaneously enabling six types of logic gate operations. This multi-functionality increases computational density by eliminating the need for separate logic gate circuits, allowing in-memory computing within the same compact area.
Data Source
AI summary
An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.