Dynamic Clock Divider Reconfiguration Without Glitches or Clock Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock reconfiguration methods, such as phase-locked loops (PLL) and counters, result in clock loss and glitches when reconfiguring clock signals on-the-fly, leading to non-operational or incorrect digital system performance due to reset states and spurious signals.
Innovation Solution
A system and method for dynamically reconfiguring multiple clock output signals using dynamic reconfigurable clock dividers, an AND logic gate, and an interface, which maintain current frequency and phase until a complete cycle is finished, then implement changes without clock loss or glitches, allowing for seamless reconfiguration of frequency, phase, and spread spectrum settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a phase-locked loop (PLL) is used for clock reconfiguration, then clock frequency and phase can be adjusted, but clock loss occurs during reset state transitions
Solution Approach 1:
The system prepares reconfiguration parameters in advance and loads them into the PLL before the actual reconfiguration event. This preliminary loading allows the PLL to switch to new frequency/phase settings without entering a reset state, as the new parameters are already staged and ready for immediate implementation when triggered.
Solution Approach 2:
The patent introduces an intermediary reconfiguration mechanism that mediates between the desired clock settings and the PLL operation. This intermediary layer manages the transition process, ensuring that frequency and phase changes occur without forcing the PLL into a reset state, thereby maintaining continuous clock output.
2Adaptability or versatility
If a counter is used for clock reconfiguration, then frequency and phase can be varied, but glitches or spurious signals occur during transitions
Solution Approach 1:
The system maintains continuous counter operation during reconfiguration by using dual counters or a counter with seamless transition capability. One counter operates while the other is being reconfigured, ensuring that the clock signal continues without interruption and without generating glitches from counter reset or reload operations.
Solution Approach 2:
Reconfiguration parameters for the counter are prepared and validated in advance before the actual transition. This preliminary preparation ensures that when the counter does switch to new settings, the transition is clean and free from spurious signals, as all parameters are pre-checked and staged correctly.
3Adaptability or versatility
If spread spectrum settings are changed in a PLL, then spectral distribution can be adjusted, but the PLL must be paused in reset state
Solution Approach 1:
Spread spectrum parameters are loaded and configured in advance within the PLL structure before the reconfiguration event is triggered. This preliminary configuration allows the spread spectrum settings to be changed without pausing the PLL, as the new parameters are already staged and can be activated immediately when the reconfiguration trigger occurs.
Solution Approach 2:
The system implements dynamic reconfiguration capability where spread spectrum settings can be adjusted on-the-fly without static reset states. The PLL maintains its operational state while parameters are dynamically updated, allowing continuous frequency modulation characteristic of spread spectrum operation without interruption.
Data Source
AI summary
A system is provided for dynamically reconfiguring clock output signals, without clock loss and glitches. The system includes an oscillator generating a clock input signal, first and second dynamic reconfigurable clock dividers, an AND logic gate and an interface. The first and second dynamic reconfigurable clock dividers include counters that output first and second clock output signals having multiple periodic cycles, respectively, and cycle complete signals in response to completion of each periodic cycle. The AND logic gate outputs an aggregated cycle complete signal in response to the cycle complete signals from the first and second dynamic reconfigurable clock dividers. The interface provides reconfiguration commands to the first dynamic reconfigurable clock divider changing frequency and/or phase of the first clock output signal. The first counter maintains the frequency and phase until receiving the aggregated cycle complete signal from the AND logic gate, and then implementing the changed frequency and/or phase.