Hierarchical Wordline Decoder for Higher-Density Memory Arrays
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Solution Overview
Problem
Current memory compilers face limitations in increasing memory density due to design efforts and performance changes, restricting the maximum number of rows per bit line to 256, necessitating a method to enhance density up to 1024 rows with minimal design effort.
Innovation Solution
Implementing area-efficient, scalable wordline decoder designs that use two pre-decoders for each memory circuitry, allowing for doubling of memory density by doubling row numbers while maintaining a fixed column number, with similar logic and critical timings to reduce extra design effort and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of rows per bit line is increased beyond 256 to achieve higher memory density, then memory density is improved, but design effort and complexity increase significantly
Solution Approach 1:
The decoder is segmented into a two-level hierarchy: pre-decoders that handle row address decoding and a main decoder that handles column address decoding. This segmentation allows the system to scale to higher row counts by adding pre-decoder stages without proportionally increasing the complexity of the main decoder, thereby enabling memory density expansion while controlling design effort.
Solution Approach 2:
The patent introduces an additional decoding dimension by adding pre-decoder stages that process row addresses separately from the main decoder that processes column addresses. This dimensional separation transforms the single-level decoding approach into a two-level hierarchical structure, enabling scalable expansion to 1024 rows per bit line while maintaining manageable complexity through modular design.
2Quantity of substance
If the number of rows per bit line is increased to 1024 to enhance memory density, then memory capacity is improved, but area overhead increases
Solution Approach 1:
The pre-decoder and main decoder are merged into an integrated hierarchical decoding structure where the pre-decoder outputs feed directly into the main decoder. This merging allows shared control logic and signal paths, reducing the total area overhead compared to completely separate decoding systems, while still enabling the expansion to 1024 rows per bit line through the hierarchical organization.
Data Source
AI summary
Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.