Switch-Controlled Ring Oscillator for Sensitive NBTI Testing

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Solution Overview

Problem

Existing ring oscillator structures are not sensitive to Negative Bias Temperature Instability (NBTI) effects, leading to inaccurate measurement results and inability to predict device service life under different stress states.

Innovation Solution

A ring oscillator design incorporating a first logic gate, a second logic gate with NAND and NOR gates connected in sequence, and switch circuits to control power and ground terminals, allowing for controlled stress states and improved sensitivity to NBTI effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional ring oscillator structure is used for NBTI testing, then the device can be tested, but the structure is not sensitive to NBTI effects resulting in unapparent differences between measurement results

Engineering Contradiction:
ImproveNBTI measurement sensitivityVSAvoidservice life prediction accuracy
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The ring oscillator is segmented into multiple logic gates with different gate types (NAND, NOR) and different sizes. This segmentation allows different portions of the oscillator to exhibit different sensitivities to NBTI effects, with smaller gates showing greater sensitivity. The segmented structure enables the test to capture NBTI impacts that would be masked in a uniform oscillator design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different logic gates within the ring oscillator are designed with different local qualities - specifically different gate sizes and types. The smaller-sized gates are more sensitive to NBTI effects, while larger gates provide stability. This local quality differentiation ensures that the oscillator as a whole can detect NBTI effects through the more sensitive local regions while maintaining overall functional stability.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If uniform logic gates are used in the ring oscillator, then the structure is simple, but it cannot evaluate NBTI effects under different stress states

Engineering Contradiction:
Improvestress state evaluation capabilityVSAvoidlogic gate configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The ring oscillator incorporates logic gates with different characteristics (different sizes, different gate types) that respond dynamically to different stress conditions. Under various stress states, different gates become increasingly or decreasingly sensitive to NBTI effects, allowing the oscillator to adaptively evaluate device degradation across multiple operating conditions rather than responding uniformly.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The ring oscillator is designed with multi-functionality by incorporating both NAND and NOR gates of different sizes, enabling it to serve multiple testing purposes simultaneously. The same oscillator structure can evaluate NBTI effects under different stress states (varying voltage, temperature, and timing conditions) without requiring separate test circuits, as each gate type and size responds differently to various stressors.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12113535B2Ring oscillator and test method
Publication Date: 2024.10.08 CHANGXIN MEMORY TECH INC
  • US12113535B2 patent drawing

AI summary

Embodiments provide a ring oscillator and test method. The ring oscillator includes a first logic gate, a second logic gate, and a switch circuit. The first logic gate is configured to receive a test signal. The second logic gate includes a first NAND gate and a first NOR gate connected in sequence. An output terminal of the second logic gate is connected to an input terminal of the first logic gate, and the second logic gate is configured to receive output of the first logic gate to form a loop. The switch circuit includes a first switch circuit and a second switch circuit. The first switch circuit may be configured to control on/off of a power supply terminal of the first NAND gate and a ground terminal of the first NOR gate. The second switch circuit is configured to control on/off of a ground terminal of the first NAND gate.